Abstract: Devices and methods are provided for controlling dead-time of a direct current to direct current (DC-DC) converter. A control circuit includes a first transistor having a source/drain terminal coupled to an output voltage of the DC-DC converter configured to provide current based on the output voltage. The control circuit also includes a digital up/down counter having an output terminal electrically coupled to an input terminal of a delay cell of the DC-DC converter. A current sensing circuit of the control circuit is electrically coupled to an input terminal of the digital up/down counter configured to receive the current and drive the digital up/down counter based on the current.

Abstract: A stacked package structure and a manufacturing method thereof are provided. The stacked package structure includes an upper redistribution layer, a first chip, and an upper molding layer. The first chip is disposed on the upper redistribution layer and is electrically connected to the upper redistribution layer. The upper molding layer is disposed on the first chip and the upper redistribution layer, and is configured to package the first chip. The upper molding layer includes a recess, the recess is recessed relative to a surface of the upper molding layer away from the upper redistribution layer, and the recess is circumferentially formed around a periphery of the upper molding layer.

Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.

Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a main branch extending along a first direction on the substrate and a sub-branch extending along a second direction adjacent to the main branch. The semiconductor device also includes a first doped region overlapping the main branch and the sub-branch according to a top view and a second doped region overlapping the first doped region.

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.

Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.

Abstract: A system including a processor configured to perform generating a plurality of different layout blocks; selecting, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of a circuit; combining the selected layout blocks in accordance with the floorplan into a layout of the circuit; and storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit. Each of the plurality of layout blocks satisfies predetermined design rules and includes at least one of a plurality of different first block options associated with a first layout feature, and at least one of a plurality of different second block options associated with a second layout feature different from the first layout feature.

Abstract: A detection system and method for the migrating cell is provided. The system is configured to detect a migrating cell combined with an immunomagnetic bead. The system includes a platform, a microchannel, a magnetic field source, a coherent light source and an optical sensing module. The microchannel is configured to allow the migrating cell to flow in it along a flow direction. The magnetic field source is configured to provide magnetic force to the migrating cell combined with the immunomagnetic bead. The magnetic force includes at least one magnetic force component and the magnetic force component is opposite to the flow direction of the microchannel. The coherent light source is configured to provide the microchannel with the coherent light. The optical sensing module is configured to receive the interference light caused by the coherent light being reflected by the sample inside the microchannel.

Abstract: A DC-DC converter and a DC-DC converter operation method are provided. The DC-DC converter includes a power stage, an error amplifier, a pulse width modulation (PWM) generator, and a gate controller. The power stage includes a first transistor and a second transistor. The voltage dividers are configured to perform a voltage division on a first node of the power stage and a second node to generate a first voltage and a second voltage. The first node is an output node of the DC-DC converter and the second node is a node between the first transistor and the second transistor of the DC-DC converter. The comparator is configured to compare the first voltage and the second voltage to generate a turn-on time signal of the first transistor according to a comparison result.

Abstract: Devices and methods are provided for controlling dead-time of a direct current to direct current (DC-DC) converter. A control circuit includes a first transistor having a source/drain terminal coupled to an output voltage of the DC-DC converter configured to provide current based on the output voltage. The control circuit also includes a digital up/down counter having an output terminal electrically coupled to an input terminal of a delay cell of the DC-DC converter. A current sensing circuit of the control circuit is electrically coupled to an input terminal of the digital up/down counter configured to receive the current and drive the digital up/down counter based on the current.

Abstract: Devices and methods are provided for controlling dead-time of a direct current to direct current (DC-DC) converter. A control circuit includes a first transistor having a source/drain terminal coupled to an output voltage of the DC-DC converter configured to provide current based on the output voltage. The control circuit also includes a digital up/down counter having an output terminal electrically coupled to an input terminal of a delay cell of the DC-DC converter. A current sensing circuit of the control circuit is electrically coupled to an input terminal of the digital up/down counter configured to receive the current and drive the digital up/down counter based on the current.

Abstract: A DC-DC converter and a DC-DC converter operation method are provided. The DC-DC converter includes a power stage, an error amplifier, a pulse width modulation (PWM) generator, and a gate controller. The power stage includes a first transistor and a second transistor. The power stage is configured to generate an output at a first node. The error amplifier is configured to receive the output from the first node and generates an error signal. The PWM generator is configured to receive the error signal from the error amplifier and generates a pulse width modulation signal. The gate controller includes a plurality of voltage dividers and a comparator. The voltage dividers are configured to perform a voltage division on the first node and a second node to generate a first voltage and a second voltage. The first node is an output node of the DC-DC converter and the second node is a node between the first transistor and the second transistor of the DC-DC converter.

Abstract: A backlight module and a display device are provided. The display device includes a display panel and a backlight module. The backlight module includes a back plate, a spacer element, and an optical element. The spacer element passes through the back plate and includes a base portion, a supporting portion, a positioning portion and a first protruding portion. The base portion has a first surface and a second surface. The supporting portion is disposed on the first surface. The positioning portion is disposed on the second surface. The first protruding portion is disposed on the second surface and is located around the positioning portion. The first protruding portion has a third surface away from and parallel to the second surface. The optical element is disposed on the spacer element. A part of the back plate is located between the base portion and a part of the positioning portion.

Abstract: A backlight module and a display device are provided. The display device includes a display panel and a backlight module. The backlight module includes a back plate, a spacer element, and an optical element. The spacer element passes through the back plate and includes a base portion, a supporting portion, a positioning portion and a first protruding portion. The base portion has a first surface and a second surface. The supporting portion is disposed on the first surface. The positioning portion is disposed on the second surface. The first protruding portion is disposed on the second surface and is located around the positioning portion. The first protruding portion has a third surface away from and parallel to the second surface. The optical element is disposed on the spacer element. A part of the back plate is located between the base portion and a part of the positioning portion.

Abstract: Devices and methods are provided for controlling dead-time of a direct current to direct current (DC-DC) converter. A control circuit includes a first transistor having a source/drain terminal coupled to an output voltage of the DC-DC converter configured to provide current based on the output voltage. The control circuit also includes a digital up/down counter having an output terminal electrically coupled to an input terminal of a delay cell of the DC-DC converter. A current sensing circuit of the control circuit is electrically coupled to an input terminal of the digital up/down counter configured to receive the current and drive the digital up/down counter based on the current.

Abstract: A circuit includes a first circuit that operates at a first-circuit supply voltage value and generates at least one of a first reference voltage value or a second reference voltage value, based on a voltage rated for transistors in a second circuit. The second circuit operates at the first-circuit supply voltage value and receives a first signal and at least one of the first reference voltage value or the second reference voltage value. The first signal is configured to swing between a low voltage value and a high voltage value lower than the first-circuit supply voltage value. The second circuit keeps a voltage across two terminals of a first transistor in the second circuit below the voltage rated for the first transistor, based on the at least one of the first reference voltage value or the second voltage value.

Abstract: A tube crimper includes a front crimper including a crimper body and multiple crimper wires arranged in a U shape and defining with the crimper body a U-shaped closed space therebetween, a die block mounted in the U-shaped closed space, and a hydraulic device having a pusher inserted through the crimper body of the front crimper and connected with the die block. After insertion of the tube and connector to be crimped into the U-shaped closed space, the hydraulic device is operated to move the pusher, causing the die block and the crimper wires to crimp the tube onto the connector.

Abstract: A display device includes a display panel and a light transmission layer disposed on the display panel. The display panel has an active area having a first side and a second side opposite to the first side and outputting a main image, and an auxiliary area located outside of and distributed along the first side and outputting an auxiliary image. The light transmission layer has a bottom surface facing the active area and receiving the main image. A light entrance surface and a reflective surface are located at sides of the bottom surface corresponding to the first side for receiving the auxiliary image and to the second side while inclining outward away from the bottom surface, respectively. After entering the light entrance surface, the auxiliary image is transmitted to the reflective surface and reflected outside one side of the main image corresponding to the second side via the reflective surface.

Abstract: A circuit includes a first circuit that operates at a first-circuit supply voltage value and generates at least one of a first reference voltage value or a second reference voltage value, based on a voltage rated for transistors in a second circuit. The second circuit operates at the first-circuit supply voltage value and receives a first signal and at least one of the first reference voltage value or the second reference voltage value. The first signal is configured to swing between a low voltage value and a high voltage value lower than the first-circuit supply voltage value. The second circuit keeps a voltage across two terminals of a first transistor in the second circuit below the voltage rated for the first transistor, based on the at least one of the first reference voltage value or the second voltage value.

Abstract: A display device includes a display panel and a light transmission layer disposed on the display panel. The display panel has an active area having a first side and a second side opposite to the first side and outputting a main image, and an auxiliary area located outside of and distributed along the first side and outputting an auxiliary image. The light transmission layer has a bottom surface facing the active area and receiving the main image. A light entrance surface and a reflective surface are located at sides of the bottom surface corresponding to the first side for receiving the auxiliary image and to the second side while inclining outward away from the bottom surface, respectively. After entering the light entrance surface, the auxiliary image is transmitted to the reflective surface and reflected outside one side of the main image corresponding to the second side via the reflective surface.