Patents by Inventor Chia-Der Chang
Chia-Der Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923436Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a buffer layer between the channel layer and the substrate. The method can further include forming a recess structure in the channel layer. The recess structure can include a bottom surface over the buffer layer. The method can further include forming a first epitaxial layer over the bottom surface of the recess structure. The first epitaxial layer can include a first atomic concentration of germanium. The method can further include forming a second epitaxial layer over the first epitaxial layer. The second epitaxial layer can include a second atomic concentration of germanium greater than the first atomic concentration of germanium.Type: GrantFiled: April 1, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Heng Li, Yi-Jing Li, Chia-Der Chang
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Patent number: 11862683Abstract: The present disclosure describes a method for forming ultra-thin fins with a tapered bottom profile for improved structural rigidity and gate control characteristics. The method includes forming a fin structure that includes an epitaxial layer portion and a doped region portion surrounded by an isolation region so that a top section of the epitaxial layer portion is above the isolation region. The method also includes depositing a silicon-based layer on the top portion of the epitaxial layer above the isolation region and annealing the silicon-based layer to reflow the silicon-based layer. The method further includes etching the silicon-based layer and the fin structure above the isolation region to form a first bottom tapered profile in the fin structure above the isolation region and annealing the fin structure to form a second bottom tapered profile below the first bottom tapered profile and above the isolation region.Type: GrantFiled: November 29, 2021Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sherry Li, Chia-Der Chang, Yi-Jing Lee
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Publication number: 20230378271Abstract: The present disclosure describes a method for forming ultra-thin fins with a tapered bottom profile for improved structural rigidity and gate control characteristics. The method includes forming a fin structure that includes an epitaxial layer portion and a doped region portion surrounded by an isolation region so that a top section of the epitaxial layer portion is above the isolation region. The method also includes depositing a silicon-based layer on the top portion of the epitaxial layer above the isolation region and annealing the silicon-based layer to reflow the silicon-based layer. The method further includes etching the silicon-based layer and the fin structure above the isolation region to form a first bottom tapered profile in the fin structure above the isolation region and annealing the fin structure to form a second bottom tapered profile below the first bottom tapered profile and above the isolation region.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sherry LI, Chia-Der Chang, Yi-Jing Lee
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Publication number: 20230207649Abstract: A semiconductor device includes a substrate; a fin structure formed on a substrate; and a gate feature formed over the fin structure, the gate feature comprising a gate dielectric layer, wherein the gate dielectric layer traverses the fin structure to overlay a central portion of the fin structure and opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend beyond respective sidewalls of the gate feature and away from the central portion of the fin structure.Type: ApplicationFiled: February 23, 2023Publication date: June 29, 2023Inventors: Guan-Jie SHEN, Chia-Der Chang, Chih-Hsiung Lin
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Patent number: 11664423Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, an insulating stack formed over the substrate, a vertical structure formed through the insulating stack, a source/drain region formed over the vertical structure, and an isolation structure formed adjacent to the source/drain region and protruding the insulating stack. The source/drain region can include a first side surface and a second side surface. A lateral separation between the first side surface and the vertical structure can be greater than an other lateral separation between the second side surface and the vertical structure.Type: GrantFiled: August 18, 2020Date of Patent: May 30, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Shuo Chen, Chia-Der Chang, Yi-Jing Lee
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Patent number: 11594607Abstract: A semiconductor device includes a substrate; a fin structure formed on a substrate; and a gate feature formed over the fin structure, the gate feature comprising a gate dielectric layer, wherein the gate dielectric layer traverses the fin structure to overlay a central portion of the fin structure and opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend beyond respective sidewalls of the gate feature and away from the central portion of the fin structure.Type: GrantFiled: February 1, 2021Date of Patent: February 28, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Guan-Jie Shen, Chia-Der Chang, Chih-Hsiung Lin
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Patent number: 11521969Abstract: A semiconductor device with an isolation structure and a method of fabricating the same are disclosed. The semiconductor device includes first and second fin structures disposed on a substrate and first and second pairs of gate structures disposed on the first and second fin structures. The first end surfaces of the first pair of gate structures face second end surfaces of the second pair of gate structure. The first and second end surfaces of the first and second pair of gate structures are in physical contact with first and second sidewalls of the isolation structure, respectively. The semiconductor device further includes an isolation structure interposed between the first and second pairs of gate structures. An aspect ratio of the isolation structure is smaller than a combined aspect ratio of the first pair of gate structures.Type: GrantFiled: July 23, 2020Date of Patent: December 6, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Shuo Chen, Chia-Der Chang, Yi-Jing Lee
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Publication number: 20220367456Abstract: A semiconductor device with an isolation structure and a method of fabricating the same are disclosed. The semiconductor device includes first and second fin structures disposed on a substrate and first and second pairs of gate structures disposed on the first and second fin structures. The first end surfaces of the first pair of gate structures face second end surfaces of the second pair of gate structure. The first and second end surfaces of the first and second pair of gate structures are in physical contact with first and second sidewalls of the isolation structure, respectively. The semiconductor device further includes an isolation structure interposed between the first and second pairs of gate structures. An aspect ratio of the isolation structure is smaller than a combined aspect ratio of the first pair of gate structures.Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Shuo CHEN, Chia-Der CHANG, Yi-Jing LEE
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Publication number: 20220367633Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, an insulating stack formed over the substrate, a vertical structure formed through the insulating stack, a source/drain region formed over the vertical structure, and an isolation structure formed adjacent to the source/drain region and protruding the insulating stack. The source/drain region can include a first side surface and a second side surface. A lateral separation between the first side surface and the vertical structure can be greater than an other lateral separation between the second side surface and the vertical structure.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Shuo CHEN, Chia-Der CHANG, Yi-Jing LEE
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Publication number: 20220085167Abstract: The present disclosure describes a method for forming ultra-thin fins with a tapered bottom profile for improved structural rigidity and gate control characteristics. The method includes forming a fin structure that includes an epitaxial layer portion and a doped region portion surrounded by an isolation region so that a top section of the epitaxial layer portion is above the isolation region. The method also includes depositing a silicon-based layer on the top portion of the epitaxial layer above the isolation region and annealing the silicon-based layer to reflow the silicon-based layer. The method further includes etching the silicon-based layer and the fin structure above the isolation region to form a first bottom tapered profile in the fin structure above the isolation region and annealing the fin structure to form a second bottom tapered profile below the first bottom tapered profile and above the isolation region.Type: ApplicationFiled: November 29, 2021Publication date: March 17, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sherry Li, Chia-Der Chang, Yi-Jing Lee
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Publication number: 20220059653Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, an insulating stack formed over the substrate, a vertical structure formed through the insulating stack, a source/drain region formed over the vertical structure, and an isolation structure formed adjacent to the source/drain region and protruding the insulating stack. The source/drain region can include a first side surface and a second side surface. A lateral separation between the first side surface and the vertical structure can be greater than an other lateral separation between the second side surface and the vertical structure.Type: ApplicationFiled: August 18, 2020Publication date: February 24, 2022Applicant: Taian Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Shuo CHEN, Chia-Der Chang, Yi-Jing Lee
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Publication number: 20220045198Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a buffer layer between the channel layer and the substrate. The method can further include forming a recess structure in the channel layer. The recess structure can include a bottom surface over the buffer layer. The method can further include forming a first epitaxial layer over the bottom surface of the recess structure. The first epitaxial layer can include a first atomic concentration of germanium. The method can further include forming a second epitaxial layer over the first epitaxial layer. The second epitaxial layer can include a second atomic concentration of germanium greater than the first atomic concentration of germanium.Type: ApplicationFiled: April 1, 2021Publication date: February 10, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Heng LI, Yi-Jing Li, Chia-Der Chang
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Patent number: 11189697Abstract: The present disclosure describes a method for forming ultra-thin fins with a tapered bottom profile for improved structural rigidity and gate control characteristics. The method includes forming a fin structure that includes an epitaxial layer portion and a doped region portion surrounded by an isolation region so that a top section of the epitaxial layer portion is above the isolation region. The method also includes depositing a silicon-based layer on the top portion of the epitaxial layer above the isolation region and annealing the silicon-based layer to reflow the silicon-based layer. The method further includes etching the silicon-based layer and the fin structure above the isolation region to form a first bottom tapered profile in the fin structure above the isolation region and annealing the fin structure to form a second bottom tapered profile below the first bottom tapered profile and above the isolation region.Type: GrantFiled: April 1, 2020Date of Patent: November 30, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sherry Li, Chia-Der Chang, Yi-Jing Lee
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Patent number: 11177173Abstract: A method for forming a semiconductor device structure includes providing a substrate and forming a gate electrode on the substrate. A first contact structure is formed in and on the gate electrode. The first contact structure comprises a first portion and a second portion. The first portion is formed in the gate electrode, and the second portion is formed on the first portion.Type: GrantFiled: November 4, 2019Date of Patent: November 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Guo-Chiang Chi, Chia-Der Chang, Chih-Hung Lu, Wei-Chin Chen
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Publication number: 20210313428Abstract: The present disclosure describes a method for forming ultra-thin fins with a tapered bottom profile for improved structural rigidity and gate control characteristics. The method includes forming a fin structure that includes an epitaxial layer portion and a doped region portion surrounded by an isolation region so that a top section of the epitaxial layer portion is above the isolation region. The method also includes depositing a silicon-based layer on the top portion of the epitaxial layer above the isolation region and annealing the silicon-based layer to reflow the silicon-based layer. The method further includes etching the silicon-based layer and the fin structure above the isolation region to form a first bottom tapered profile in the fin structure above the isolation region and annealing the fin structure to form a second bottom tapered profile below the first bottom tapered profile and above the isolation region.Type: ApplicationFiled: April 1, 2020Publication date: October 7, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sherry LI, Chia-Der Chang, Yi-Jing Lee
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Publication number: 20210233906Abstract: A semiconductor device with an isolation structure and a method of fabricating the same are disclosed. The semiconductor device includes first and second fin structures disposed on a substrate and first and second pairs of gate structures disposed on the first and second fin structures. The first end surfaces of the first pair of gate structures face second end surfaces of the second pair of gate structure. The first and second end surfaces of the first and second pair of gate structures are in physical contact with first and second sidewalls of the isolation structure, respectively. The semiconductor device further includes an isolation structure interposed between the first and second pairs of gate structures. An aspect ratio of the isolation structure is smaller than a combined aspect ratio of the first pair of gate structures.Type: ApplicationFiled: July 23, 2020Publication date: July 29, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Shuo CHEN, Chia-Der CHANG, Yi-Jing LEE
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Publication number: 20210184013Abstract: A semiconductor device includes a substrate; a fin structure formed on a substrate; and a gate feature formed over the fin structure, the gate feature comprising a gate dielectric layer, wherein the gate dielectric layer traverses the fin structure to overlay a central portion of the fin structure and opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend beyond respective sidewalls of the gate feature and away from the central portion of the fin structure.Type: ApplicationFiled: February 1, 2021Publication date: June 17, 2021Inventors: Guan-Jie SHEN, Chia-Der Chang, Chih-Hsiung Lin
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Patent number: 10910479Abstract: A semiconductor device includes a substrate; a fin structure formed on a substrate; and a gate feature formed over the fin structure, the gate feature comprising a gate dielectric layer, wherein the gate dielectric layer traverses the fin structure to overlay a central portion of the fin structure and opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend beyond respective sidewalls of the gate feature and away from the central portion of the fin structure.Type: GrantFiled: May 22, 2020Date of Patent: February 2, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Guan-Jie Shen, Chia-Der Chang, Chih-Hsiung Lin
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Publication number: 20200287010Abstract: A semiconductor device includes a substrate; a fin structure formed on a substrate; and a gate feature formed over the fin structure, the gate feature comprising a gate dielectric layer, wherein the gate dielectric layer traverses the fin structure to overlay a central portion of the fin structure and opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend beyond respective sidewalls of the gate feature and away from the central portion of the fin structure.Type: ApplicationFiled: May 22, 2020Publication date: September 10, 2020Inventors: Guan-Jie SHEN, Chia-Der Chang, Chih-Hsiung Lin
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Patent number: 10763280Abstract: A semiconductor device includes a first fin field effect transistor (FinFET) device, the first FinFET device including a plurality of fins formed in a substrate, an epitaxial layer of semiconductor material formed on the fins forming non-planar source/drain regions, and a first gate structure traversing across the plurality of fins. The semiconductor device includes a second FinFET device, the second FinFET device including a substantially planar fin formed in the substrate, an epitaxial layer of the semiconductor material formed on the substantially planar fin and forming substantially planar source/drain regions, and a second gate structure traversing across the substantially planar fin.Type: GrantFiled: May 25, 2018Date of Patent: September 1, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Chen Liu, Guan-Jie Shen, Chia-Der Chang