Patents by Inventor Chia-Der Chang
Chia-Der Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10763280Abstract: A semiconductor device includes a first fin field effect transistor (FinFET) device, the first FinFET device including a plurality of fins formed in a substrate, an epitaxial layer of semiconductor material formed on the fins forming non-planar source/drain regions, and a first gate structure traversing across the plurality of fins. The semiconductor device includes a second FinFET device, the second FinFET device including a substantially planar fin formed in the substrate, an epitaxial layer of the semiconductor material formed on the substantially planar fin and forming substantially planar source/drain regions, and a second gate structure traversing across the substantially planar fin.Type: GrantFiled: May 25, 2018Date of Patent: September 1, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Chen Liu, Guan-Jie Shen, Chia-Der Chang
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Patent number: 10665686Abstract: A semiconductor device includes a fin structure, disposed on a substrate, that horizontally extends along a direction; and a gate feature comprising a gate dielectric layer and at least a first metal gate layer overlaying the gate dielectric layer, wherein the gate dielectric layer and the first metal gate layer traverse the fin structure to overlay a central portion of the fin structure and further extend along the direction to overlay at least a side portion of the fin structure that is located outside a vertical projection of a sidewall of the gate feature.Type: GrantFiled: April 8, 2019Date of Patent: May 26, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Guan-Jie Shen, Chia-Der Chang, Chih-Hsiung Lin
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Publication number: 20200066587Abstract: A method for forming a semiconductor device structure includes providing a substrate and forming a gate electrode on the substrate. A first contact structure is formed in and on the gate electrode. The first contact structure comprises a first portion and a second portion. The first portion is formed in the gate electrode, and the second portion is formed on the first portion.Type: ApplicationFiled: November 4, 2019Publication date: February 27, 2020Inventors: Guo-Chiang CHI, Chia-Der CHANG, Chih-Hung LU, Wei-Chin CHEN
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Patent number: 10468299Abstract: A method for forming a semiconductor device structure includes providing a substrate and forming a gate electrode on the substrate. A first contact structure is formed in and on the gate electrode. The first contact structure comprises a first portion and a second portion. The first portion is formed in the gate electrode, and the second portion is formed on the first portion.Type: GrantFiled: March 2, 2018Date of Patent: November 5, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Guo-Chiang Chi, Chia-Der Chang, Chih-Hung Lu, Wei-Chin Chen
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Publication number: 20190237555Abstract: A semiconductor device includes a fin structure, disposed on a substrate, that horizontally extends along a direction; and a gate feature comprising a gate dielectric layer and at least a first metal gate layer overlaying the gate dielectric layer, wherein the gate dielectric layer and the first metal gate layer traverse the fin structure to overlay a central portion of the fin structure and further extend along the direction to overlay at least a side portion of the fin structure that is located outside a vertical projection of a sidewall of the gate feature.Type: ApplicationFiled: April 8, 2019Publication date: August 1, 2019Inventors: Guan-Jie Shen, Chia-Der Chang, Chih-Hsiung Lin
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Patent number: 10276680Abstract: A semiconductor device includes a fin structure, disposed on a substrate, that horizontally extends along a direction; and a gate feature comprising a gate dielectric layer and at least a first metal gate layer overlaying the gate dielectric layer, wherein the gate dielectric layer and the first metal gate layer traverse the fin structure to overlay a central portion of the fin structure and further extend along the direction to overlay at least a side portion of the fin structure that is located outside a vertical projection of a sidewall of the gate feature.Type: GrantFiled: July 18, 2017Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Guan-Jie Shen, Chia-Der Chang, Chih-Hsiung Lin
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Publication number: 20190027569Abstract: A semiconductor device includes a fin structure, disposed on a substrate, that horizontally extends along a direction; and a gate feature comprising a gate dielectric layer and at least a first metal gate layer overlaying the gate dielectric layer, wherein the gate dielectric layer and the first metal gate layer traverse the fin structure to overlay a central portion of the fin structure and further extend along the direction to overlay at least a side portion of the fin structure that is located outside a vertical projection of a sidewall of the gate feature.Type: ApplicationFiled: July 18, 2017Publication date: January 24, 2019Inventors: Guan-Jie SHEN, Chia-Der CHANG, Chih-Hsiung LIN
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Publication number: 20190006392Abstract: A semiconductor device includes a first fin field effect transistor (FinFET) device, the first FinFET device including a plurality of fins formed in a substrate, an epitaxial layer of semiconductor material formed on the fins forming non-planar source/drain regions, and a first gate structure traversing across the plurality of fins. The semiconductor device includes a second FinFET device, the second FinFET device including a substantially planar fin formed in the substrate, an epitaxial layer of the semiconductor material formed on the substantially planar fin and forming substantially planar source/drain regions, and a second gate structure traversing across the substantially planar fin.Type: ApplicationFiled: May 25, 2018Publication date: January 3, 2019Inventors: Chien-Chen LIU, Guan-Jie Shen, Chia-Der Chang
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Patent number: 10115596Abstract: A method of fabricating a metal gate structure in a semiconductor device is disclosed. The method comprises removing a dummy poly gate, removing IL oxide and STI using a dry etch process and a wet lateral etch process to form a T-shape void in the semiconductor device, and depositing metal gate material in the T-shape void to form a T-shape structure in a metal gate line-end. A semiconductor device fabricated from a process that included the removal of a dummy poly gate is disclosed. The semiconductor device comprises an OD fin and a metal gate fabricated above a section of the OD fin and adjacent to a side section of the OD fin. The metal gate has a T-shape structure in a metal gate line-end. The T-shape structure was formed by removing IL oxide and STI using a dry and a wet lateral etch process to form a T-shape void.Type: GrantFiled: August 31, 2017Date of Patent: October 30, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Chih Lin, Chien-Hung Yeh, Guan-Jie Shen, Chia-Der Chang
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Patent number: 10090397Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate stack positioned over the semiconductor substrate. The semiconductor device structure includes spacers positioned over sidewalls of the gate stack. The semiconductor device structure includes a first protective layer positioned between the gate stack and the spacers and between the spacers and the semiconductor substrate. The semiconductor device structure includes a second protective layer positioned between the spacers and the first protective layer. The first protective layer and the second protective layer include different materials.Type: GrantFiled: August 29, 2014Date of Patent: October 2, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Ming-Chang Lee, Chia-Der Chang, Chih-Hung Lu, Chung-Tsun Sun, Chung-Wei Hung
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Patent number: 10083959Abstract: A method includes forming a gate, a first dielectric layer, a first contact structure, and a second contact structure over a substrate. The first contact structure and the second contact structure are over a source region and a drain region respectively. The first dielectric layer surrounds the gate, the first contact structure, and the second contact structure. The method includes forming a second dielectric layer over the first dielectric layer. The second dielectric layer has an opening exposing the gate, the first contact structure, and the second contact structure. A conductive layer is formed in the opening to electrically connect the gate to the first contact structure and the second contact structure.Type: GrantFiled: August 25, 2017Date of Patent: September 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Chang Lee, Chung-Tsun Sun, Chia-Der Chang
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Patent number: 10056462Abstract: The present disclosure provides a semiconductor structure includes a semiconductor layer having a surface, and an interlayer dielectric (ILD) defining a metal gate over the surface of the semiconductor layer. The metal gate includes a high-k dielectric layer, a capping layer, and a work function metal layer. A thickness of the capping layer sidewall distal to a corner of the capping layer, is substantially thinner than a thickness which is around center of the capping layer bottom. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate recess, forming a high-k dielectric layer, forming a first capping layer, forming a second capping layer on the first capping layer, removing or thinning down the first capping layer sidewall, and removing the second capping layer.Type: GrantFiled: August 13, 2014Date of Patent: August 21, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chih Hsiung Lin, Chia-Der Chang, Fan-Yi Hsu, Pin-Cheng Hsu
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Publication number: 20180197775Abstract: A method for forming a semiconductor device structure includes providing a substrate and forming a gate electrode on the substrate. A first contact structure is formed in and on the gate electrode. The first contact structure comprises a first portion and a second portion. The first portion is formed in the gate electrode, and the second portion is formed on the first portion.Type: ApplicationFiled: March 2, 2018Publication date: July 12, 2018Inventors: Guo-Chiang CHI, Chia-Der CHANG, Chih-Hung LU, Wei-Chin CHEN
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Patent number: 9941152Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a metal gate stack formed over the semiconductor substrate. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the metal gate stack includes a metal gate electrode. The semiconductor device further includes a metal oxide structure formed over the insulating layer and in direct contact with the insulating layer. The metal oxide structure includes an oxidized material of the metal gate electrode.Type: GrantFiled: February 6, 2017Date of Patent: April 10, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Jia Hsieh, Chih-Lin Wang, Chia-Der Chang
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Patent number: 9923056Abstract: A method of fabricating a MOSFET with an undoped channel is disclosed. The method comprises fabricating on a substrate a semiconductor structure having a dummy poly gate, dummy interlayer (IL) oxide, and a doped channel. The method further comprises removing the dummy poly gate and the dummy IL oxide to expose the doped channel, removing the doped channel from an area on the substrate, forming an undoped channel for the semiconductor structure at the area on the substrate, and forming a metal gate for the semiconductor structure. Removing the dummy poly gate may comprise dry and wet etch operations. Removing the dummy IL oxide may comprise dry etch operations. Removing the doped channel may comprise anisotropic etch operations on the substrate. Forming an undoped channel may comprise applying an epitaxial process to grow the undoped channel. The method may further comprise growing IL oxide above the undoped channel.Type: GrantFiled: December 2, 2016Date of Patent: March 20, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chih-Hsiung Lin, Chia-Der Chang, Jung-Ting Chen, Tai-Yuan Wang
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Patent number: 9911650Abstract: A method for forming a semiconductor device structure includes providing a substrate and forming a gate electrode on the substrate. A first contact structure is formed in and on the gate electrode. The first contact structure comprises a first portion and a second portion. The first portion is formed in the gate electrode, and the second portion is formed on the first portion.Type: GrantFiled: October 20, 2016Date of Patent: March 6, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Guo-Chiang Chi, Chia-Der Chang, Chih-Hung Lu, Wei-Chin Chen
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Publication number: 20180061977Abstract: A method of fabricating a metal gate structure in a semiconductor device is disclosed. The method comprises removing a dummy poly gate, removing IL oxide and STI using a dry etch process and a wet lateral etch process to form a T-shape void in the semiconductor device, and depositing metal gate material in the T-shape void to form a T-shape structure in a metal gate line-end. A semiconductor device fabricated from a process that included the removal of a dummy poly gate is disclosed. The semiconductor device comprises an OD fin and a metal gate fabricated above a section of the OD fin and adjacent to a side section of the OD fin. The metal gate has a T-shape structure in a metal gate line-end. The T-shape structure was formed by removing IL oxide and STI using a dry and a wet lateral etch process to form a T-shape void.Type: ApplicationFiled: August 31, 2017Publication date: March 1, 2018Inventors: Chieh-Chih LIN, Chien-Huang YEH, Guan-Jie SHEN, Chia-Der CHANG
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Publication number: 20170352655Abstract: A method includes forming a gate, a first dielectric layer, a first contact structure, and a second contact structure over a substrate. The first contact structure and the second contact structure are over a source region and a drain region respectively. The first dielectric layer surrounds the gate, the first contact structure, and the second contact structure. The method includes forming a second dielectric layer over the first dielectric layer. The second dielectric layer has an opening exposing the gate, the first contact structure, and the second contact structure. A conductive layer is formed in the opening to electrically connect the gate to the first contact structure and the second contact structure.Type: ApplicationFiled: August 25, 2017Publication date: December 7, 2017Inventors: Ming-Chang LEE, Chung-Tsun SUN, Chia-Der CHANG
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Patent number: 9780213Abstract: A method of fabricating a metal gate structure in a semiconductor device is disclosed. The method comprises removing a dummy poly gate, removing IL oxide and STI using a dry etch process and a wet lateral etch process to form a T-shape void in the semiconductor device, and depositing metal gate material in the T-shape void to form a T-shape structure in a metal gate line-end. A semiconductor device fabricated from a process that included the removal of a dummy poly gate is disclosed. The semiconductor device comprises an OD fin and a metal gate fabricated above a section of the OD fin and adjacent to a side section of the OD fin. The metal gate has a T-shape structure in a metal gate line-end. The T-shape structure was formed by removing IL oxide and STI using a dry and a wet lateral etch process to form a T-shape void.Type: GrantFiled: April 15, 2014Date of Patent: October 3, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Chih Lin, Chien-Hung Yeh, Guan-Jie Shen, Chia-Der Chang
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Patent number: 9748232Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first source region and a first drain region. The semiconductor device structure includes a first gate over the substrate and between the first source region and the first drain region. The semiconductor device structure includes a first contact structure over the first source region. The first contact structure is electrically connected to the first source region. The semiconductor device structure includes a second contact structure over the first drain region. The second contact structure is electrically connected to the first drain region. The semiconductor device structure includes a conductive layer electrically connecting the first gate to the first contact structure and the second contact structure.Type: GrantFiled: March 25, 2015Date of Patent: August 29, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Chang Lee, Chung-Tsun Sun, Chia-Der Chang