Abstract: A semiconductor device includes a first conductor structure extending along a lateral direction. The semiconductor device includes a first memory film that extends along a vertical direction and is in contact with the first conductor structure. The semiconductor device includes a first semiconductor film that extends along the vertical direction and is in contact with the first memory film. Ends of the first semiconductor film align with ends of the first memory film, respectively. The semiconductor device includes a second conductor structure extending along the vertical direction. The semiconductor device includes a third conductor structure extending along the vertical direction. The semiconductor device includes a fourth conductor structure extending along the vertical direction. The second and fourth conductor structures are coupled to the ends of the first semiconductor film, and the third conductor structure is coupled to a portion of the first semiconductor film between its ends.

Abstract: A ferroelectric memory device and a memory array are provided. The ferroelectric memory device includes a word line; a pair of source/drain electrodes, a channel layer, a work function layer and a ferroelectric layer. The source/drain electrodes are disposed at opposite sides of the word line, and elevated from the word line. The channel layer has a bottom planar portion and wall portions. The bottom planar portion extends along a top surface of the word line, and opposite ends of the bottom planar portion are connected to sidewalls of the source/drain electrodes through opposite ones of the wall portions. The work function layer is electrically connected to the word line, and extends along the bottom planar portion and the wall portions of the channel layer. The ferroelectric layer separates the channel layer from the work function layer.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure, disposed over a substrate; a ferroelectric material, disposed over the gate structure; a source structure and a drain structure, disposed above the ferroelectric material; an isolation, surrounding the source structure and the drain structure; and an oxide semiconductor, surrounding a portion of the isolation between the source structure and the drain structure. A method of manufacturing the semiconductor structure is also provided.

Abstract: A semiconductor device includes a substrate, a gate dielectric layer, a gate electrode, a field plate, a source electrode and a drain electrode. The gate dielectric layer is disposed on the substrate and includes a first portion having a first thickness, a second portion having a second thickness, and a third portion having a third thickness. The first, second and third thicknesses are different from each other, and the first thickness is smaller than the second and third thicknesses. The gate electrode is disposed on the first portion of the gate dielectric layer. The field plate is separated from and electrically coupled to the gate electrode, and is disposed on the second and third portions of the gate dielectric layer. The source and drain electrodes are disposed on the sides of the gate electrode and the field plate, respectively.

Abstract: A semiconductor device includes a first transistor, a second transistor, and a memory component. The first transistor includes a first silicon layer, a high-k gate dielectric layer above the first silicon layer, a first metal gate above the high-k gate dielectric layer, and first source/drain regions within the first silicon layer. The second transistor includes a second silicon layer, a first silicon oxide layer above the second silicon layer, a plurality of first doped silicon gates above the first silicon oxide layer, a plurality of second doped silicon gates above the first silicon oxide layer and alternately arranged with the plurality of first doped silicon gates, and second source/drain regions within the second silicon layer. The memory component is above the first and second transistors, and electrically coupled to the second source or drain region.

Abstract: A method (of writing to a ferroelectric field-effect transistor (FeFET) configured as a 2-bit storage device that stores two bits, wherein the FeFET includes a first source/drain (S/D) terminal, a second S/D terminal, a gate terminal and a ferroelectric layer, a second bit being at a first end of the ferroelectric layer, the first end being proximal to the first S/D terminal) includes: setting the second bit to a logical 1 value, the setting a second bit including applying a gate voltage to the gate terminal, and applying a first source/drain voltage to the second S/D terminal; and wherein the first source/drain voltage is lower than the gate voltage.

Abstract: A memory structure includes a plurality of memory cells arranged in an array. Each of the memory cells includes a memory region, a word line portion disposed on a first surface of the memory region, a first conductive block disposed on a second surface of the memory region opposite to the first surface, a second conductive block disposed on the second surface of the memory region, and a third conductive block disposed on the second surface of the memory region such that the third conductive block is disposed between and separated from the first conductive block and the second conductive block.

Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.

Abstract: A wireless communication method and apparatus for handling radio resource collision are provided. The wireless communication method includes receiving a Radio Resource Control (RRC) configuration indicating a first Control Resource Set (CORESET) pool index associated with a Physical Uplink Control Channel (PUCCH) designated to carry Uplink Control Information (UCI); determining whether the PUCCH overlaps one or more Physical Uplink Shared Channels (PUSCHs) in time domain; after determining that the PUCCH overlaps at least one of the one or more PUSCHs in the time domain, multiplexing the UCI on a particular PUSCH of the one or more PUSCHs that is associated with the first CORESET pool index; and transmitting the UCI via the particular PUSCH.

Abstract: An electronic package is provided, in which a mesh structure is disposed between a circuit structure and an electronic element to increase the shunt path of current. Therefore, when the electronic element is used as an electrode pad of a power contact, the current can be passed through a conductive sheet of the circuit structure via the mesh structure, such that the power loss can be reduced and the IR drop of the electronic element can meet the requirements.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.

Abstract: A semiconductor device includes a plurality of ferroelectric memory cells arranged over a substrate. Each of the plurality of ferroelectric memory cells includes: a first conductive structure extending along a first lateral direction and having a central portion and a pair of side portions, the side portions respectively extending away from the central portion along a second lateral direction perpendicular to the first lateral direction; a ferroelectric layer disposed above the first conductive structure and in contact with the central portion of the first conductive structure; a channel film disposed above a portion of the ferroelectric layer; a second conductive structure disposed above and in contact with the channel film; and a third conductive structure disposed above and in contact with the channel film.

Abstract: A test method is configured to test a chip on a circuit under test, wherein the circuit under test further includes a DC-DC converter. The test method includes the operations of: generating a test pulse signal; filtering the test pulse signal to generate a first test DC voltage to the DC-DC converter, wherein the DC-DC converter transforms the first test DC voltage to a second test DC voltage and transmits the second test DC voltage to the chip; and extracting an output signal of the chip to determine a performance of the chip, wherein the chip generates the output signal according to the second test DC voltage.

Abstract: A method for transferring a container configured to hold at least one article used in semiconductor fabrication is provided. The method includes moving a transferring mechanism to a first position that is adjacent to the original space; producing an image of an edge of the container that is adjacent to the original space using an optical receiver before the container is moved to a destination space; and performing an image analysis of the image to determine whether to move the container to the destination space.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: A method for transferring a container configured to hold at least one article used in semiconductor fabrication is provided. The method includes moving a transferring mechanism to a first position that is adjacent to the original space; producing an image of an edge of the container that is adjacent to the original space using an optical receiver before the container is moved to a destination space; and performing an image analysis of the image to determine whether to move the container to the destination space.