Abstract: A semiconductor device includes a first memory cell that includes: a first conductor structure extending along a first lateral direction; a first portion of a first memory film wrapping around a first portion of the first conductor structure; a first semiconductor film wrapping around the first portion of the first memory film; a second conductor structure extending along a vertical direction and coupled to a first sidewall of the first semiconductor film, wherein the first sidewall faces toward or away from a second lateral direction perpendicular to the first lateral direction; and a third conductor structure extending along the vertical direction and coupled to a second sidewall of the first semiconductor film, wherein the second sidewall faces toward or away from the second lateral direction.

Abstract: A semiconductor device includes a first transistor, a second transistor, and a memory component. The first transistor includes a first silicon layer, a high-k gate dielectric layer above the first silicon layer, a first metal gate above the high-k gate dielectric layer, and first source/drain regions within the first silicon layer. The second transistor includes a second silicon layer, a first silicon oxide layer above the second silicon layer, a plurality of first doped silicon gates above the first silicon oxide layer, a plurality of second doped silicon gates above the first silicon oxide layer and alternately arranged with the plurality of first doped silicon gates, and second source/drain regions within the second silicon layer. The memory component is above the first and second transistors, and electrically coupled to the second source or drain region.

Abstract: A wafer map recognition method using artificial intelligence includes obtaining wafer maps of a plurality of wafers; performing an unsupervised algorithm on the wafer map of each wafer in the plurality of wafers to generate a feature data set for the corresponding wafer map; and performing a clustering algorithm according to a plurality of feature data sets for the plurality of wafer maps to find a wafer map with a potential defect.

Abstract: A semiconductor memory device includes first and second memory units, and first and second staircase vias. The first memory unit includes two first source/bit line portions separated from each other, a first word line surrounding the first source/bit line portions, a first memory film surrounding the first word line, and a first channel region between the first memory film and the first source/bit line portions. The second memory unit is disposed over the first memory unit, and includes two second source/bit line portions separated from each other, a second word line surrounding the second source/bit line portions, a second memory film surrounding the second word line, and a second channel region between the second memory film and the second source/bit line portions. The first and second staircase vias respectively penetrate the first and second memory films, and are respectively and electrically connected to the first and second word lines.

Abstract: A method for facilitating streamer interaction with a viewer includes extracting a history topic based on an activity record of the viewer; calculating a score of each of the history topics based on at least one parameter; and generating a topic suggestion based on the history topic and the score which is corresponding to the history topic, and providing the topic suggestion to the streamer. The method is suitable for providing a topic suggestion (or interact topic suggestion) with respect to the viewer to the streamer via a live-streaming platform executed by a computing device. Thereby, the method can be used for facilitating streamer interaction with viewers and provides an appropriate topic suggestion. In addition, a computing device and a computer-readable storage medium which are capable of implementing the method are also provided.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

Abstract: One aspect of this description relates to a semiconductor device. In some embodiments, the semiconductor device includes a first drain/source structure extending in a first direction, a second drain/source structure extending the first direction and spaced from the first drain/source structure in a second direction perpendicular to the first direction, a third drain/source structure extending in the first direction and spaced from the second drain/source structure in the second direction, a first bit line disposed over the first drain/source structure in the first direction, a common select line that includes a portion disposed over the second drain/source structure in the first direction, a second bit line disposed over the third drain/source structure in the first direction, and a charge storage layer coupled to at least a first sidewall of each of the first drain/source structure, the second drain/source structure, and the third drain/source structure.

Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, and which includes a substrate, bit lines, bit line contacts, a gate structure, a first oxidized interface layer, and a second oxidized interface layer. The bit lines are disposed on the substrate, and the bit line contacts are disposed below the bit lines. The gate structure is disposed on the substrate, wherein each bit line and the gate structure respectively include a semiconductor layer, a conductive layer, and a covering layer stacked from bottom to top. The first oxidized interface layer is disposed between each bit line contact and the semiconductor layer of each bit line. The second oxidized interface layer is disposed within the semiconductor layer of the gate structure, wherein a topmost surface of the first oxidized interface layer is higher than a topmost surface of the second oxidized interface layer.

Abstract: A display panel and a pixel circuit thereof are provided. A pulse width signal generator turns on a charge sharing switch during a light-emitting period, and performs charge sharing with a control end of a positive feedback switch of a positive feedback circuit, so as to control the positive feedback switch to provide a positive feedback voltage to the pulse width signal generator to increase a voltage at an output end of the pulse width signal generator and thus to accelerate a rising speed of a voltage for controlling a driving current generator to provide a driving current.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: A test method is configured to test a chip on a circuit under test, wherein the circuit under test further includes a DC-DC converter. The test method includes the operations of: generating a test pulse signal; filtering the test pulse signal to generate a first test DC voltage to the DC-DC converter, wherein the DC-DC converter transforms the first test DC voltage to a second test DC voltage and transmits the second test DC voltage to the chip; and extracting an output signal of the chip to determine a performance of the chip, wherein the chip generates the output signal according to the second test DC voltage.

Abstract: A method for transferring a container configured to hold at least one article used in semiconductor fabrication is provided. The method includes moving a transferring mechanism to a first position that is adjacent to the original space; producing an image of an edge of the container that is adjacent to the original space using an optical receiver before the container is moved to a destination space; and performing an image analysis of the image to determine whether to move the container to the destination space.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: A method for transferring a container configured to hold at least one article used in semiconductor fabrication is provided. The method includes moving a transferring mechanism to a first position that is adjacent to the original space; producing an image of an edge of the container that is adjacent to the original space using an optical receiver before the container is moved to a destination space; and performing an image analysis of the image to determine whether to move the container to the destination space.

Abstract: A method for transferring a container for holding one or more articles is provided. The method includes transferring the container using a transferring mechanism to a position which is adjacent to a destination space. The method further includes recording an image of the destination space before the container is deposited to the destination space. The method also includes performing an image analysis of the image and determining if the container is able to be sent to the destination space according to a result of the image analysis of the image.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: A method for transferring a container for holding one or more articles is provided. The method includes transferring the container using a transferring mechanism to a position which is adjacent to a destination space. The method further includes recording an image of the destination space before the container is deposited to the destination space. The method also includes performing an image analysis of the image and determining if the container is able to be sent to the destination space according to a result of the image analysis of the image.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.