Abstract: A memory device is provided. The memory device includes a memory cell array having a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of columns include a first plurality of memory cells connected to a first bit line and a second bit line. A pre-charge circuit is connected to the memory cell array. The pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end. A pre-charge assist circuit is connected to the memory cell array. The pre-charge assist circuit pre-charges each of the first bit line and the second bit line from a second end, the second end being opposite the first end.

Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

Abstract: A semiconductor device and method of fabricating thereof where the device includes a fin structure between a first isolation region and a second isolation region. A first source/drain feature is formed over a recessed portion of the first fin structure. The first source/drain feature interfaces a top surface of the first isolation region for a first distance and interfaces the top surface of the second isolation region for a second distance. The first distance is different than the second distance. The source/drain feature is offset in a direction.

Abstract: A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.

Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

Abstract: A method of forming a semiconductor structure includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, forming cladding layers along sidewalls of the fin structure, forming a dummy gate stack over the cladding layers, and forming source/drain (S/D) features in the fin structure and adjacent to the dummy gate stack. The method further includes removing the dummy gate stack to form a gate trench adjacent to the S/D features, removing the cladding layers to form first openings along the sidewalls of the fin structure, where the first openings extend to below the stack, removing the first semiconductor layers to form second openings between the second semiconductor layers and adjacent to the first openings, and subsequently forming a metal gate stack in the gate trench, the first openings, and the second openings.

Abstract: A four times contacted poly pitch (4CPP) static random-access memory (SRAM) cell layout is disclosed that forms six SRAM transistors from one OD region and four poly lines at a frontside of a substrate and provides a double-sided routing structure for word lines, bit lines, and/or voltage lines. For example, a vertical SRAM is disclosed that stacks transistors, vertically, to facilitate scaling needed for advanced IC technology nodes and improve memory performance. The vertical SRAM further includes a double-sided routing structure, which facilitates placement of bit lines, word lines, and voltage lines in a backside metal one (M1) layer and/or a frontside M1 layer to minimize line capacitance and line resistance.

Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

Abstract: A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.

Abstract: Semiconductor structures and methods are provided. A method according to the present disclosure includes forming a first channel member, a second channel member directly over the first channel member, and a third channel member directly over the second channel member, depositing a first metal layer around each of the first channel member, the second channel member, and the third channel member, removing the first metal layer from around the second channel member and the third channel member while the first channel member remains wrapped around by the first metal layer, after the removing of the first metal layer, depositing a second metal layer around the second channel member and the third channel member, removing the second metal layer from around the third channel member, and after the removing of the second metal layer, depositing a third metal layer around the third channel member.

Abstract: A method and structure for modulating a threshold voltage of a device. In various embodiments, a fin extending from a substrate is provided. In some embodiments, the fin includes a plurality of semiconductor channel layers defining a channel region for a P-type transistor. In some examples, a gate dielectric is formed wrapping around each of the plurality of semiconductor channel layers of the P-type transistor. In some cases, a P-type work function (PWF) metal gate cap is formed wrapping around the gate dielectric. In various embodiments, the PWF metal gate cap merges between adjacent semiconductor channel layers of the plurality of channel layers. Additionally, in some examples, the PWF metal gate cap includes a plurality of nitrogen-containing layers.

Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

Abstract: A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.

Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor having a first gate dielectric layer, a second transistor having a second gate dielectric layer, and a third transistor having a third gate dielectric layer. The first gate dielectric layer includes a first concentration of a dipole layer material, the second gate dielectric layer includes a second concentration of the dipole layer material, and the third gate dielectric layer includes a third concentration of the dipole layer material. The dipole layer material includes lanthanum oxide, aluminum oxide, or yittrium oxide. The first concentration is greater than the second concentration and the second concentration is greater than the third concentration.

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.

Abstract: Memory systems are provided. In an embodiment, a memory device includes a word line driver coupled to a plurality of word lines, a recycle multiplexer coupled to a plurality of bit lines and a plurality of bit line bars, a memory cell array, and a compensation word line driver. The memory cell array includes a first end adjacent the word line driver, a second end away from the word line driver, and a plurality of memory cells. The compensation word line driver is disposed adjacent the second end of the memory cell array and coupled to the plurality of word lines. The recycle multiplexer is configured to selectively couple one or more of the plurality of bit lines or one or more of the plurality of bit line bars to the compensation word line driver.

Abstract: Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof are disclosed herein. An exemplary metal gate includes a first portion, a second portion, and a third portion. The second portion is disposed between the first portion and the third portion. The first portion includes a first gate dielectric layer, a first p-type work function layer, and a first n-type work function layer. The second portion includes a second gate dielectric layer and a second p-type work function layer. The third portion includes a third gate dielectric layer, a third p-type work function, and a second n-type work function layer. The second p-type work function layer separates the first n-type work function layer from the second n-type work function layer, such that the first n-type work function layer does not share an interface with the second n-type work function layer.

Abstract: A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor having a first gate dielectric layer, a second transistor having a second gate dielectric layer, and a third transistor having a third gate dielectric layer. The first gate dielectric layer includes a first concentration of a dipole layer material, the second gate dielectric layer includes a second concentration of the dipole layer material, and the third gate dielectric layer includes a third concentration of the dipole layer material. The dipole layer material includes lanthanum oxide, aluminum oxide, or yttrium oxide. The first concentration is greater than the second concentration and the second concentration is greater than the third concentration.