Abstract: Memory systems are provided. In an embodiment, a memory device includes a word line driver coupled to a plurality of word lines, a recycle multiplexer coupled to a plurality of bit lines and a plurality of bit line bars, a memory cell array, and a compensation word line driver. The memory cell array includes a first end adjacent the word line driver, a second end away from the word line driver, and a plurality of memory cells. The compensation word line driver is disposed adjacent the second end of the memory cell array and coupled to the plurality of word lines. The recycle multiplexer is configured to selectively couple one or more of the plurality of bit lines or one or more of the plurality of bit line bars to the compensation word line driver.

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.

Abstract: Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof are disclosed herein. An exemplary metal gate includes a first portion, a second portion, and a third portion. The second portion is disposed between the first portion and the third portion. The first portion includes a first gate dielectric layer, a first p-type work function layer, and a first n-type work function layer. The second portion includes a second gate dielectric layer and a second p-type work function layer. The third portion includes a third gate dielectric layer, a third p-type work function, and a second n-type work function layer. The second p-type work function layer separates the first n-type work function layer from the second n-type work function layer, such that the first n-type work function layer does not share an interface with the second n-type work function layer.

Abstract: A semiconductor device and method of fabricating thereof where the device includes a fin structure between a first isolation region and a second isolation region. A first source/drain feature is formed over a recessed portion of the first fin structure. The first source/drain feature interfaces a top surface of the first isolation region for a first distance and interfaces the top surface of the second isolation region for a second distance. The first distance is different than the second distance. The source/drain feature is offset in a direction.

Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

Abstract: A memory device includes a memory array having a plurality of memory cells. Each of the plurality of memory cells includes a first word line to apply a first signal to select the each of the plurality of memory cells to read data from or write the data to the each of the plurality of memory cells, a second word line to apply a second signal to select the each of the plurality of memory cells to read the data from or write the data to the each of the plurality of memory cells, and a bit line to read the data from the each of the plurality of memory cells or provide the data to write to the each of the plurality of memory cells upon selecting the each of the plurality of memory cells by at least one of the first word line or the second word line.

Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor having a first gate dielectric layer, a second transistor having a second gate dielectric layer, and a third transistor having a third gate dielectric layer. The first gate dielectric layer includes a first concentration of a dipole layer material, the second gate dielectric layer includes a second concentration of the dipole layer material, and the third gate dielectric layer includes a third concentration of the dipole layer material. The dipole layer material includes lanthanum oxide, aluminum oxide, or yttrium oxide. The first concentration is greater than the second concentration and the second concentration is greater than the third concentration.

Abstract: An SRAM structure is provided. The SRAM structure includes a plurality of first well regions with a first doping type, a second well region with a second doping type, a plurality of first well pick-up regions, a plurality of second well pick-up regions and a plurality of memory cells. The first well regions are formed in a semiconductor substrate. The second well region is formed in the semiconductor substrate. The first well pick-up regions are formed in the first well regions. The second well pick-up regions are formed in the second well region. Each of the memory cells is disposed on two adjacent first well regions and a portion of the second well region between the two adjacent first well regions. Each of the first well pick-up regions is disposed between two adjacent second well pick-up regions.

Abstract: Fin-based well straps are disclosed for improving performance of memory arrays, such as static random access memory arrays. An exemplary well strap cell is disposed between a first memory cell and a second memory cell. The well strap cell includes a p-well, a first n-well, and a second n-well disposed in a substrate. The p-well, the first n-well, and the second n-well are configured in the well strap cell such that a middle portion of the well strap cell is free of the first n-well and the second n-well along a gate length direction. The well strap cell further includes p-well pick up regions to the p-well and n-well pick up regions to the first n-well, the second n-well, or both. The p-well has an I-shaped top view along the gate length direction.

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a boost circuit configured to output a first negative voltage at a fist output terminal, and an adjustment circuit configured to couple the first negative voltage to a second negative voltage higher than the first negative voltage. The adjustment circuit can include a transistor, and a second output terminal electrically connected to the first output terminal. The transistor can include a first source/drain terminal, a second source/drain terminal, and a gate terminal. The first source/drain terminal can be electrically coupled to the second output terminal. The second source/drain terminal can be electrically connected to a voltage source. The gate terminal can be electrically connected to a ground voltage supply.

Abstract: A SRAM array is provided. The SRAM array includes a first bit cell array and a second bit cell array arranged along a first direction, and a strap cell arranged along a second direction and positioned between the first bit cell array and the second bit cell array along the first direction. The strap cell includes a first P-type well region, two first N-type well regions, a second N-type well region. The two first N-type well regions are separated by the first P-type well region in the first direction, and the second N-type well region and one of the two first N-type well regions are separated by the first P-type well region in the second direction. The strap cell further includes a deep N-type well region underlying the two first N-type well regions and the second N-type well region.

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a boost circuit configured to output a first negative voltage at a first output terminal, and an adjustment circuit configured to couple the first negative voltage to a second negative voltage higher than the first negative voltage. The adjustment circuit can include a transistor, and a second output terminal electrically connected to the first output terminal. The transistor can include a first source/drain terminal, a second source/drain terminal, and a gate terminal. The first source/drain terminal can be electrically coupled to the second output terminal. The second source/drain terminal can be electrically connected to a voltage source. The gate terminal can be electrically connected to a ground voltage supply.

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a boost circuit configured to output a first negative voltage at a first output terminal, and an adjustment circuit configured to couple the first negative voltage to a second negative voltage higher than the first negative voltage. The adjustment circuit can include a transistor, and a second output terminal electrically connected to the first output terminal. The transistor can include a first source/drain terminal, a second source/drain terminal, and a gate terminal. The first source/drain terminal can be electrically coupled to the second output terminal. The second source/drain terminal can be electrically connected to a voltage source. The gate terminal can be electrically connected to a ground voltage supply.

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.

Abstract: Memory systems are provided. In an embodiment, a memory device includes a word line driver coupled to a plurality of word lines, a recycle multiplexer coupled to a plurality of bit lines and a plurality of bit line bars, a memory cell array, and a compensation word line driver. The memory cell array includes a first end adjacent the word line driver, a second end away from the word line driver, and a plurality of memory cells. The compensation word line driver is disposed adjacent the second end of the memory cell array and coupled to the plurality of word lines. The recycle multiplexer is configured to selectively couple one or more of the plurality of bit lines or one or more of the plurality of bit line bars to the compensation word line driver.

Abstract: A SRAM array is provided. The SRAM array includes a first bit cell array and a second bit cell array arranged along a first direction, and a strap cell arranged along a second direction and positioned between the first bit cell array and the second bit cell array along the first direction. The strap cell includes a first P-type well region, two first N-type well regions, a second N-type well region. The two first N-type well regions are separated by the first P-type well region in the first direction, and the second N-type well region and one of the two first N-type well regions are separated by the first P-type well region in the second direction. The strap cell further includes a deep N-type well region underlying the two first N-type well regions and the second N-type well region.

Abstract: A SRAM array is provided, including a first bit cell array and a second bit cell array arranged along a first direction; a strap cell arranged in a second direction and positioned between the first bit cell array and the second bit cell array along the first direction. The strap cell includes a first strap column, a second strap column, a doped P-type region, a doped N-type region, and a deep N-type well region. The first strap column includes a first P-type well region and two first N-type well regions adjacent opposite sides of the first P-type well region along the first direction. The second strap column is adjacent to the first strap column along the second direction. The second strap column includes a second N-type well region and two second P-type well regions adjacent opposite sides of the second N-type well region along the first direction.

Abstract: An SRAM structure is provided. The SRAM structure includes a plurality of first well regions with a first doping type, a second well region with a second doping type, a plurality of first well pick-up regions, a plurality of second well pick-up regions and a plurality of memory cells. The first well regions are formed in a semiconductor substrate. The second well region is formed in the semiconductor substrate. The first well pick-up regions are formed in the first well regions. The second well pick-up regions are formed in the second well region. Each of the memory cells is disposed on two adjacent first well regions and a portion of the second well region between the two adjacent first well regions. Each of the first well pick-up regions is disposed between two adjacent second well pick-up regions.

Abstract: A SRAM array is provided, including a first bit cell array and a second bit cell array arranged along a first direction; a strap cell arranged in a second direction and positioned between the first bit cell array and the second bit cell array along the first direction. The strap cell includes a first strap column, a second strap column, a doped P-type region, a doped N-type region, and a deep N-type well region. The first strap column includes a first P-type well region and two first N-type well regions adjacent opposite sides of the first P-type well region along the first direction. The second strap column is adjacent to the first strap column along the second direction. The second strap column includes a second N-type well region and two second P-type well regions adjacent opposite sides of the second N-type well region along the first direction.