Abstract: A user equipment (UE) and a method for wireless communication are provided. The method includes: receiving a radio resource control (RRC) configuration from a base station (BS); determining whether a first parameter is configured in the RRC configuration; receiving first downlink control information (DCI) from the BS, the first DCI including a first field indicating a first Hybrid Automatic Repeat Request (HARD) process identifier (ID); determining that a number of bits in the first field is a default number in a case that the first parameter is not configured in the RRC configuration; and determining that the number of bits in the first field is a specific number greater than the default number in a case that the first parameter is configured in the RRC configuration.

Abstract: This disclosure provides a user equipment (UE) and methods for channel state information (CSI) compression. Processing circuitry of the UE obtain a plurality of first channel matrices that each indicates CSI of a communication channel between the UE and a respective one of multiple transmission-reception-points (TRPs). The processing circuitry compresses each of the plurality of first channel matrices into a respective feature vector through one or more convolutional neural networks (CNNs), and concatenates the plurality of feature vectors into a joint feature vector. The processing circuitry compresses the joint feature vector into a compressed joint feature vector through one or more fully connected neural networks (FCNNs).

Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked, the first and second semiconductor layers having different material compositions; forming a sacrificial gate structure over the fin structure; forming a gate spacer on sidewalls of the sacrificial gate structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure and the gate spacer, thereby forming an S/D trench; laterally etching the first semiconductor layers through the S/D trench, thereby forming recesses; selectively depositing an insulating layer on surfaces of the first and second semiconductor layers exposed in the recesses and the S/D trench, but not on sidewalls of the gate spacer; and growing an S/D epitaxial feature in the S/D trench, thereby trapping air gaps in the recesses.

Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.

Abstract: A device includes a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer. The second dielectric layer and the first dielectric layer have different material compositions. A metal-insulator-metal (MIM) structure is embedded in the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer. The third dielectric layer and the second dielectric layer have different material compositions. The first dielectric layer or the third dielectric layer may contain silicon nitride (SiN), the second dielectric layer may contain silicon oxide (SiO2).

Abstract: A method includes providing a semiconductor structure having a metal gate structure (MG), gate spacers disposed on sidewalls of the MG, and a source/drain (S/D) feature disposed adjacent to the gate spacers; forming a first metal layer over the S/D feature and between the gate spacers; recessing the first metal layer to form a trench; forming a dielectric layer on sidewalls of the trench; forming a second metal layer over the first metal layer in the trench, wherein sidewalls of the second metal layer are defined by the dielectric layer; and forming a contact feature over the MG to contact the MG.

Abstract: A method and a user equipment (UE) for resource selection approach adaptation are provided. The method includes receiving, from a Base Station (BS), a first Sidelink (SL) transmission resource pool configuration and a second SL transmission resource pool configuration; performing a first resource selection on a first SL transmission resource pool by applying a first resource selection approach; receiving, from the BS, an adaption indication that a second resource selection approach is to be applied; performing, during a transition period between a time at which the adaption indication is received and a time at which the second resource selection approach is applied, a second resource selection on a second SL transmission resource pool by applying a third resource selection approach; and performing, after the transition period, a third resource selection on the first SL transmission resource pool by applying the second resource selection approach indicated by the adaption indication.

Abstract: The disclosure provides a method of channel scheduling for narrowband Internet of Things (NB-IoT) in a non-terrestrial network (NTN) and a user equipment using the same. The method includes: transmitting an uplink signal ending in a first subframe; determining a monitoring window starting from a second subframe according to the first subframe and a time offset; and monitoring a downlink signal corresponding to the uplink signal according to the monitoring window.

Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate having a front-side surface and a back-side surface, and an electrical device formed over the front-side surface of a substrate. The package structure includes a dielectric layer formed below and in direct contact with the back-side surface of the substrate, and a first optical device formed in the dielectric layer. The package structure also includes a protective layer formed below or above the first optical device; and an electro-optic effect material layer formed in the protective layer.

Abstract: A semiconductor device with reduced contact resistance is provided. The semiconductor device includes a substrate having a channel region and a source/drain region, a source/drain contact structure over the source/drain region, a conductive structure over the source/drain contact structure, an interlayer dielectric (ILD) layer surrounding the conductive structure and source/drain contact structure, a dielectric liner between the ILD layer and the conductive structure, and a diffusion barrier between the dielectric liner and the conductive structure.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

Abstract: A package structure is provided, and includes an interposer, a control unit, a plurality of computing units, a signal transmission layer, and an electric-optical material. The control unit is bonded to the interposer. The computing units are disposed around and connected to the control unit. The signal transmission layer is formed in the control unit and the computing units. The electric-optical material is formed in the control unit and the computing units, and the electric-optical material overlaps the signal transmission layer.

Abstract: A package structure and a formation method are provided. The method includes forming electrical devices over a substrate and forming an interconnect structure over front sides of the electrical devices. The method also includes thinning the substrate and forming backside through vias connecting to backsides of the electrical devices. The method also includes attaching a waveguide layer over backsides of the electrical devices and forming conductive vias through the waveguide layer and electrically connected to the backside through vias.

Abstract: A method of fabricating a semiconductor device is described. The method includes forming a plurality of fins over a substrate, and forming dummy gates patterned over the fins. Each dummy gate has a spacer on sidewalls of the patterned dummy gates. The method also includes forming recesses in the fins by using the patterned dummy gates as a mask, forming a passivation layer over the fins and in the recesses in the fins, and patterning the passivation layer to leave a remaining passivation layer in some of the recesses in the fins.

Abstract: A semiconductor device includes semiconductor channel members vertically stacked over a substrate, a gate stack wrapping around the semiconductor channel members, a gate spacer disposed on sidewalls of the gate stack, a source/drain (S/D) epitaxial feature in contact with the semiconductor channel members, and an insulating layer interposing the S/D epitaxial feature and the gate stack. The insulating layer, the S/D epitaxial feature, and the gate spacer collectively define air gaps stacked between adjacent ones of the semiconductor channel members.

Abstract: A method of fabricating a semiconductor device is described. A plurality of fins is formed over a substrate. Dummy gates are formed patterned over the fins, each dummy gate having a spacer on sidewalls of the patterned dummy gates. Recesses are formed in the fins using the patterned dummy gates as a mask. A passivation layer is formed over the fins and in the recesses in the fins. The passivation layer is patterned to leave a remaining passivation layer only in some of the recesses in the fins. Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation layer.

Abstract: In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.

Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.

Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.