Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

Abstract: Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.

Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.

Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.

Abstract: Adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions, and methods of fabricating adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. One or more gate stacks is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between adjacent ones of the first epitaxial source or drain structures and between adjacent ones of the second epitaxial source or drain structures.

Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.

Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.

Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.

Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.

Abstract: Gate endcap architectures having relatively short vertical stack, and methods of fabricating gate endcap architectures having relatively short vertical stack, are described. In an example, an integrated circuit structure includes a first semiconductor fin along a first direction. A second semiconductor fin is along the first direction. A trench isolation material is between the first semiconductor fin and the second semiconductor fin. The trench isolation material has an uppermost surface below a top of the first and second semiconductor fins. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin and is along the first direction. The gate endcap isolation structure is on the uppermost surface of the trench isolation material.

Abstract: An apparatus comprising at least one transistor in a first area of a substrate and at least one transistor in a second area, a work function material on a channel region of each of the at least one transistor, wherein an amount of work function material in the first area is different than an amount of work function material in the second area. A method comprising depositing a work function material and a masking material on at least one transistor body in a first area and at least one in a second area; removing less than an entire portion of the masking material so that the portion of the work function material that is exposed in the first area is different than that exposed in the second area; removing the exposed work function material; and forming a gate electrode on each of the at least one transistor bodies.

Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

Abstract: A transistor including a source and a drain each formed in a substrate; a channel disposed in the substrate between the source and drain, wherein the channel includes opposing sidewalls with a distance between the opposing sidewalls defining a width dimension of the channel and wherein the opposing sidewalls extend a distance below a surface of the substrate; and a gate electrode on the channel. A method of forming a transistor including forming a source and a drain in an area of a substrate; forming a source contact on the source and a drain contact on the drain; after forming the source contact and the drain contact, forming a channel in the substrate in an area between the source and drain, the channel including a body having opposing sidewalls separated by a length dimension; and forming a gate contact on the channel.

Abstract: Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.