Abstract: A backlight module of an illuminated keyboard device includes a circuit board and a plurality of light-emitting elements. The circuit board has a top surface and a bottom surface opposite to the top surface. The top surface has a plurality of key assembling regions. Each of the key assembling regions has a stress release hole defined through the top surface and the bottom surface. The light-emitting elements are respectively disposed on the key assembling regions. Each of the light-emitting elements includes a main body and a conductive portion connected to the main body. The conductive portion is electrically connected to the circuit board, and the stress release hole is adjacent to the conductive portion of each of the light-emitting elements.

Abstract: A keyboard includes a base plate, a plurality of keys and a backlight module. The base plate has a short axis direction and a long axis direction. The keys are disposed on the base plate along the long axis direction, and the keys are arranged to form a plurality of rows. The backlight module is disposed on the base plate and includes a shielding sheet, a light guide plate and a reflecting sheet. The light guide plate is disposed on a lower surface of the shielding sheet. The light guide plate includes a plurality of long openings, and each of the long openings has at least one long side. The long side is parallel to the long axis direction, and each of the long openings has a central axis. The central axis is located between two adjacent rows on which the keys are disposed.

Abstract: A power throttling engine includes a register configured to receive a power throttling signal. The power throttling engine further includes a decoder configured to generate a vector based on a value of the power throttling signal. The value of the power throttling signal is an amount of power throttling of a device. The power throttling engine further includes a clock gating logic configured to receive the vector and further configured to receive a clocking signal. The clock gating logic is configured to remove clock edges of the clocking signal based on the vector to generate a throttled clocking signal.

Abstract: A new approach contemplates systems and methods to support control of power consumption of a memory on a chip by throttling port access requests to the memory via a memory arbiter based on a one or more programmable parameters. The memory arbiter is configured to restrict the number of ports being used to access the memory at the same time to be less than the available ports of the memory, thereby enabling adaptive power control of the chip. Two port throttling schemes are enabled—strict port throttling, which throttles the number of ports granted for memory access to be no more than a user-configured maximum throttle port number, and leaky bucket port throttling, which throttles the number of ports granted for the memory access down to be within a range based on a number of credit tokens maintained in a credit register.

Abstract: A rehabilitation system based on brainwave control includes a rehabilitation device, a brainwave device and a control unit. The rehabilitation device includes a power unit and a rehabilitation unit. The control unit is coupled with the rehabilitation device and the brainwave device. In a state where the power unit provides the predetermined output to control the rehabilitation unit to drive the rehabilitation part to move, the control unit receives the brainwave signal and determines whether the brainwave signal is lower than a stimulation threshold. In a state where the brainwave signal is lower than the stimulation threshold, the control unit sends an adjustment signal to control the power unit to adjust the predetermined output to drive the rehabilitation unit to move.

Abstract: Control logic circuitry stores packets in a queue in an order in which the packets are received. A head entry of the queue corresponds to an oldest packet in the order. The control logic circuitry receives flow control information corresponding to multiple target devices including at least a first target device and a second target device. The control logic circuitry determines, using the flow control information, whether the oldest packet stored in the head entry can be transferred to the first target device, and in response to determining that the oldest packet stored in the head entry cannot be transferred to the first target device, i) selects an other entry with an other packet behind the head entry according to the order, and ii) transfers the other packet to the second target device prior to transferring the oldest packet in the head entry to the first target device.

Abstract: A method of converting a data stored in a memory from a first format to a second format is disclosed. The method includes extending a number of bits in the data stored in a double data rate (DDR) memory by one bit to form an extended data. The method further includes determining whether the data stored in the DDR is signed or unsigned data. Moreover, responsive to determining that the data is signed, a sign value is added to the most significant bit of the extended data and the data is copied to lower order bits of the extended data. Responsive to determining that the data is unsigned, the data is copied to lower order bits of the extended data and the most significant bit is set to an unsigned value, e.g., zero. The extended data is stored in an on-chip memory (OCM) of a processing tile of a machine learning computer array.

Abstract: A keyboard includes a base plate and a backlight module. The base plate has a short axis direction and a long axis direction, and the base plate includes at least one long slit. The long slit is disposed on the base plate along the short axis direction. The backlight module is disposed on the base plate. The backlight module includes a shielding sheet, a light guide plate and a reflecting sheet. An upper surface of the shielding sheet faces toward the base plate. The light guide plate is disposed on a lower surface of the shielding sheet. The reflecting sheet is disposed below the light guide plate. The reflecting sheet includes a plurality of first slits. When the length of the base plate is adjusted along the long axis direction, the reflective sheet is adjusted and moved along with the base plate by expansion of the first slits.

Abstract: A keyboard includes a base plate, a plurality of keys and a backlight module. The base plate has a short axis direction and a long axis direction. The keys are disposed on the base plate along the long axis direction, and the keys are arranged to form a plurality of rows. The backlight module is disposed on the base plate and includes a shielding sheet, a light guide plate and a reflecting sheet. The light guide plate is disposed on a lower surface of the shielding sheet. The light guide plate includes a plurality of long openings, and each of the long openings has at least one long side. The long side is parallel to the long axis direction, and each of the long openings has a central axis. The central axis is located between two adjacent rows on which the keys are disposed.

Abstract: A keyboard includes a base plate, a plurality of keys and a backlight module. The base plate has a short axis direction and a long axis direction. The keys are disposed on the base plate. The backlight module is disposed on the base plate and includes a shielding sheet, a light guide plate and a reflecting sheet. The light guide plate is disposed on a lower surface of the shielding sheet. The light guide plate includes a plurality of light guide structures corresponding to the keys respectively. Each of the light guide structures includes a ring portion and at least one bend line portion. The bend line portion connects to the ring portion, and the ring portion is formed by a plurality of bending portions. The reflecting sheet is disposed below the light guide plate.

Abstract: A method of converting a data stored in a memory from a first format to a second format is disclosed. The method includes extending a number of bits in the data stored in a double data rate (DDR) memory by one bit to form an extended data. The method further includes determining whether the data stored in the DDR is signed or unsigned data. Moreover, responsive to determining that the data is signed, a sign value is added to the most significant bit of the extended data and the data is copied to lower order bits of the extended data. Responsive to determining that the data is unsigned, the data is copied to lower order bits of the extended data and the most significant bit is set to an unsigned value, e.g., zero. The extended data is stored in an on-chip memory (OCM) of a processing tile of a machine learning computer array.

Abstract: A system includes a plurality of cores. Each core includes a processing unit, an on-chip memory (OCM), and an idle detector unit. Data is received and stored in the OCM. Instructions are received to process data in the OCM. The core enters an idle mode if the idle detector unit detects that the core has been idle for a first number of clocking signals. The core receives a command to process when in idle mode and transitions from the idle mode to an operational mode. A number of no operation (No-Op) commands is inserted for each time segment. A No-Op command prevents the core from processing instructions for a certain number of clocking signals. A number of No-Op commands inserted for a first time segment is greater than a number of No-Op commands inserted for a last time segment. After the last time segment no No-Op command is inserted.

Abstract: A semiconductor device includes a dielectric interposer, a first redistribution layer, a second redistribution layer and conductive structures. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first redistribution layer and the second redistribution layer. Each of the conductive structures has a tapered profile. A width of each of the conductive structures proximal to the first redistribution layer is narrower than a width of each of the conductive structure proximal to the second redistribution layer.

Abstract: A processing unit to support inference acceleration for machine learning (ML) comprises an inline post processing unit configured to accept and maintain one or more lookup tables for performing each of one or more non-linear mathematical operations. The inline post processing unit is further configured to accept data from a set of registers maintaining output from a processing block instead of streaming the data from an on-chip memory (OCM), perform the one or more non-linear mathematical operations on elements of the data from the processing block via their corresponding lookup tables, and stream post processing result of the one or more non-linear mathematical operations back to the OCM after the one or more non-linear mathematical operations are complete.

Abstract: A semiconductor device includes a dielectric interposer, a first interconnection layer, an electronic component, a plurality of electrical conductors and a plurality of conductive structures. The dielectric interposer has a first surface and a second surface opposite to the first surface. The first interconnection layer is over the first surface of the dielectric interposer. The electronic component is over and electrically connected to the first interconnection layer. The electrical conductors are over the second surface of the dielectric interposer. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first interconnection layer and the electrical conductors.

Abstract: A multi-dimensional mesh architecture is proposed to support transmitting data packets from one source to a plurality of destinations in multicasting or broadcasting modes. Each data packet to be transmitted to the destinations carries a destination mask, wherein each bit in the destination mask represents a corresponding destination processing block in the mesh architecture the data packet is sent to. The data packet traverses through the mesh architecture based on a routing scheme, wherein the data packet first traverses in a first direction across a first set of processing blocks and then traverses in a second direction across a second set of processing blocks to the first destination. During the process, the data packet is only replicated when it reaches a splitting processing block where the paths to different destinations diverge. The original and the replicated data packets are then routed in different directions until they reach their respective destinations.

Abstract: A power throttling engine includes a register configured to receive a power throttling signal. The power throttling engine further includes a decoder configured to generate a vector based on a value of the power throttling signal. The value of the power throttling signal is an amount of power throttling of a device. The power throttling engine further includes a clock gating logic configured to receive the vector and further configured to receive a clocking signal. The clock gating logic is configured to remove clock edges of the clocking signal based on the vector to generate a throttled clocking signal.

Abstract: A method includes receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data. The method includes determining whether the received input data is a qnan (quiet not-a-number) or whether the received input data is an snan (signaling not-a-number) prior to performing the floating point arithmetic operation. The method also includes converting a value of the received input data to a modified value prior to performing the floating point arithmetic operation if the received input data is either qnan or snan, wherein the converting eliminates special handling associated with the floating point arithmetic operation on the input data being either qnan or snan.

Abstract: A method includes receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data. The method also includes determining whether the received input data is positive infinity or negative infinity prior to performing the floating point arithmetic operation. The method further includes converting a value of the received input data to a modified value prior to performing the floating point arithmetic operation if the received input data is positive infinity or negative infinity.

Abstract: A method includes receiving a first input data and a second input data at a floating point arithmetic operating unit, wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the first input data and the second input data. The method further includes determining whether the first input data is a qnan (quiet not-a-number) or whether the first input data is an snan (signaling not-a-number) prior to performing the floating point arithmetic operation. A value of the first input data is modified prior to performing the floating point arithmetic operation if the first input data is either qnan or snan, wherein the converting eliminates special handling associated with the floating point arithmetic operation on the first input data being either qnan or snan.