Abstract: A programmable hardware architecture for machine learning (ML) is proposed, which includes at least a host, a memory, a core, a data streaming engine, a instruction-streaming engine, and an interference engine. The core interprets a plurality of ML commands for a ML operation and/or data received from the host and coordinate activities of the engines based on the data in the received ML commands. The instruction-streaming engine translates the ML commands received from the core and provide a set of programming instructions to the data streaming engine and the inference engines based on the translated parameters. The data steaming engine sends one or more data streams to the inference engine in response to the received programming instructions. The inference engine then processes the data streams received from the data stream engine according to the programming instructions received from the instruction-streaming engine.

Abstract: A programmable hardware system for machine learning (ML) includes a core and a streaming engine. The core receives a plurality of commands and a plurality of data from a host to be analyzed and inferred via machine learning. The core transmits a first subset of commands of the plurality of commands that is performance-critical operations and associated data thereof of the plurality of data for efficient processing thereof. The first subset of commands and the associated data are passed through via a function call. The streaming engine is coupled to the core and receives the first subset of commands and the associated data from the core. The streaming engine streams a second subset of commands of the first subset of commands and its associated data to an inference engine by executing a single instruction.

Abstract: A programmable hardware system for machine learning (ML) includes a core and an inference engine. The core receives commands from a host. The commands are in a first instruction set architecture (ISA) format. The core divides the commands into a first set for performance-critical operations, in the first ISA format, and a second set of performance non-critical operations, in the first ISA format. The core executes the second set to perform the performance non-critical operations of the ML operations and streams the first set to inference engine. The inference engine generates a stream of the first set of commands in a second ISA format based on the first set of commands in the first ISA format. The first set of commands in the second ISA format programs components within the inference engine to execute the ML operations to infer data.

Abstract: A semiconductor structure includes a first substrate including a first surface and a second surface opposite to the first surface; a first die disposed over the second surface of the first substrate; a plurality of first conductive bumps disposed between the first die and the first substrate; a molding disposed over the first substrate and surrounding the first die and the plurality of first conductive bumps; a second substrate disposed below the first surface of the first substrate; a plurality of second conductive bumps disposed between the first substrate and the second substrate; and a second die disposed between the first substrate and the second substrate.

Abstract: A semiconductor device includes a dielectric interposer, a first interconnection layer, an electronic component, a plurality of electrical conductors and a plurality of conductive structures. The dielectric interposer has a first surface and a second surface opposite to the first surface. The first interconnection layer is over the first surface of the dielectric interposer. The electronic component is over and electrically connected to the first interconnection layer. The electrical conductors are over the second surface of the dielectric interposer. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first interconnection layer and the electrical conductors.

Abstract: A semiconductor structure includes a first substrate including a first surface and a second surface opposite to the first surface; a first die disposed over the second surface of the first substrate; a plurality of first conductive bumps disposed between the first die and the first substrate; a molding disposed over the first substrate and surrounding the first die and the plurality of first conductive bumps; a second substrate disposed below the first surface of the first substrate; a plurality of second conductive bumps disposed between the first substrate and the second substrate; and a second die disposed between the first substrate and the second substrate.

Abstract: A lower limb rehabilitation system includes an analysis platform, a smart insole, a motion sensor and a brain wave sensor. The analysis platform has a deep learning model. The smart insole generates plural pressure signals through plural pressure sensors of a pressure sensing film. The smart insole includes a processing unit controlling a transmission unit to transmit the pressure signals to the analysis platform. The processing unit is connected to a power supply unit. The motion sensor generates a motion signal. The brain wave sensor is coupled with the analysis platform and detects a brain wave signal. The analysis platform inputs the pressure signals, the motion signal and the brain wave signal into the deep learning model for analyzing a gait. The deep learning model analyzes whether the gait is correct. The analysis platform generates a warning message if the gait is analyzed to be incorrect.

Abstract: A keyswitch device includes a bottom plate, a membrane circuit board, a keyswitch assembly, and at least one spacer structure. The membrane circuit board is located over the bottom plate and has a trigger zone. The membrane circuit board is configured to generate a trigger signal when the trigger zone is pressed. The keyswitch assembly is disposed over the membrane circuit board and configured to press the trigger zone. The spacer structure is disposed between the bottom plate and the membrane circuit board and substantially aligned with the peripheral edge of the trigger zone. The spacer structure is configured to separate the bottom plate and the membrane circuit board by a distance.

Abstract: A key device includes a bottom plate, a light guiding membrane switch, and a keycap. The light guiding membrane switch is disposed on the bottom plate and includes a lower membrane layer, an upper membrane layer, a light guiding spacing layer, a reflective layer, and an adhering layer. The upper membrane layer is disposed above the lower membrane layer and farther from the bottom plate than the lower membrane layer. The light guiding spacing layer is disposed between the lower membrane layer and the upper membrane layer and includes opposite upper and lower surfaces. The reflective layer is securely fastened on the upper surface. The adhering layer is adhered between the reflective layer and the upper membrane layer, and a position and a shape of the adhering layer correspond to a position and a shape of the reflective layer.

Abstract: A key device includes a bottom plate, a light guiding membrane switch, and a keycap. The light guiding membrane switch is disposed on the bottom plate and includes a lower membrane layer, an upper membrane layer, a light guiding spacing layer, a reflective layer, and an adhering layer. The upper membrane layer is disposed above the lower membrane layer and farer from the bottom plate than the lower membrane layer. The light guiding spacing layer is disposed between the lower membrane layer and the upper membrane layer and includes opposite upper and lower surfaces. The reflective layer is securely fastened on the upper surface. The adhering layer is adhered between the reflective layer and the upper membrane layer, and a position and a shape of the adhering layer correspond to a position and a shape of the reflective layer.

Abstract: A keyswitch device includes a bottom plate, a membrane circuit board, a keyswitch assembly, and at least one spacer structure. The membrane circuit board is located over the bottom plate and has a trigger zone. The membrane circuit board is configured to generate a trigger signal when the trigger zone is pressed. The keyswitch assembly is disposed over the membrane circuit board and configured to press the trigger zone. The spacer structure is disposed between the bottom plate and the membrane circuit board and substantially aligned with the peripheral edge of the trigger zone. The spacer structure is configured to separate the bottom plate and the membrane circuit board by a distance.

Abstract: A light-emitting keyboard includes a membrane circuit board including a lower layer, an upper layer and a light-guiding spacer layer arranged between lower layer, an upper layer and defining therein a tapered through hole, a substrate holding membrane circuit board, a key assembly including key cap, a linkage coupled between key cap and substrate and an elastic element supported between key cap and membrane circuit board, and a light source for emitting light into the light-guiding spacer layer. The light-guiding spacer layer uses its thickness to isolate the lower layer and the upper layer and its tapered through hole to provide room for a triggering stroke for enabling the upper layer to electrically contact the lower layer second circuit in producing a corresponding switching signal each time the key assembly is pressed. Thus, the light-emitting keyboard achieves the characteristics of low profile, low manufacturing cost, and simple assembly process.

Abstract: The present invention provides a cross-linking non-fluoro hydrophobic aqueous polyurethane dispersion, which is produced by selecting a compound comprising alcohols, amines, acids, saturated or unsaturated (double-bonded or epoxidized) aliphatic long chain carbon-carbon groups or polydimethylsiloxane comprising alcohol groups, amines, oxosilane to be reacted with IPDI to obtain a PU prepolymer; adding a compound having tertiary amines to neutralize the carboxylic acid of PU prepolymer and adding water to disperse the PU prepolymer; and adding a ambient temperature cross-linking agent to obtain a cross-linking hydrophobic aqueous PU dispersion of the present invention. The hydrophobic aqueous-based PU resin has no fluorine which is friendly to the environment, and may further self cross-links on its applications on fabric, paper, wood, glass and metal surfaces, respectively on drying at ambient temperature which is energy saving process.

Abstract: A method for maintaining address mapping for a flash memory module is disclosed including: recording a first set of addresses corresponding to a first set of sequential logical addresses in a first section of a first addressing block; recording a second set of addresses corresponding to a second set of sequential logical addresses in a second section of the first addressing block; recording a third set of addresses corresponding to a third set of sequential logical addresses in a first section of a second addressing block; and recording a fourth set of addresses corresponding to a fourth set of sequential logical addresses in a second section of the second addressing block; wherein the second set of logical addresses is successive to the first set of logical addresses, and the third set of logical addresses is successive to the second set of logical addresses.

Abstract: A data storage apparatus has a transmission interface, a nonvolatile memory and a controller. The controller records a non-completed flag. When the controller starts a card opening process, the nonvolatile memory is configured under card opening, and the non-completed flag is set non-completed status. When the controller receives a format command form the transmission interface, the nonvolatile memory is formatted and the non-completed flag is set as completed status. When the controller receives a write command, the write data are scrambled before being written to the nonvolatile memory. When in non-completed status, when the controller receives a read command from the transmission interface, no matter whether the data corresponding to the requested address are scrambled, the data are descrambled and descrambled are provided via the transmission interface.

Abstract: A method for maintaining address mapping for a flash memory module is disclosed including: recording a first set of addresses corresponding to a first set of sequential logical addresses in a first section of a first addressing block; recording a second set of addresses corresponding to a second set of sequential logical addresses in a second section of the first addressing block; recording a third set of addresses corresponding to a third set of sequential logical addresses in a first section of a second addressing block; and recording a fourth set of addresses corresponding to a fourth set of sequential logical addresses in a second section of the second addressing block; wherein the second set of logical addresses is successive to the first set of logical addresses, and the third set of logical addresses is successive to the second set of logical addresses.

Abstract: A disk array system and a data processing method are provided. The data processing method is applied to the disk array system. The disk array system is a redundancy array of independent disk 0 (RAID 0) system. The disk array system includes a plurality of disks. The data processing method includes: receiving a reading command; determining whether to divide the reading command to a plurality of reading command segments according to the reading command; and assigning the reading command to a corresponding disk of the disks to read data stored in the corresponding disk accordingly when it is determined that the reading command is not divided.

Abstract: A disk array system and a data processing method are provided. The data processing method is applied to the disk array system. The disk array system includes a first disk and a second disk. The data processing method includes: receiving a reading command, wherein the reading, command includes a data starting address; determining to assign the reading command to the first disk or the second disk according to the data starting address of the reading command and a stripe size; and reading corresponding data according to the reading command from the first disk or the second disk which receives the reading command.

Abstract: A semiconductor device includes a substrate, first strain-inducing source and drain structures, a first gate structure, a first channel region, second strain-inducing source and drain structures, a second gate structure, and a second channel region. At least one of the first strain-inducing source and drain structures has a first proximity to the first channel region. At least one of the second strain-inducing source and drain structures has a second proximity to the second channel region. The second proximity is different from the first proximity.

Abstract: A light-emitting keyboard includes a membrane circuit board including a lower layer, an upper layer and a light-guiding spacer layer arranged between lower layer, an upper layer and defining therein a tapered through hole, a substrate holding membrane circuit board, a key assembly including key cap, a linkage coupled between key cap and substrate and an elastic element supported between key cap and membrane circuit board, and a light source for emitting light into the light-guiding spacer layer. The light-guiding spacer layer uses its thickness to isolate the lower layer and the upper layer and its tapered through hole to provide room for a triggering stroke for enabling the upper layer to electrically contact the lower layer second circuit in producing a corresponding switching signal each time the key assembly is pressed. Thus, the light-emitting keyboard achieves the characteristics of low profile, low manufacturing cost, and simple assembly process.