Patents by Inventor Chia-Hsing Yu

Chia-Hsing Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6556051
    Abstract: An apparatus for providing both supports including synchronous dynamic random access memory module and the double data rate dynamic random access memory module is provided. A motherboard can support standard synchronous dynamic random access memory and dual data rate dynamic random access memory by using the disable and enable functions of the terminator. The invention reduces manufacturing production waste due to complex fabrication process of memory module. In addition, the trouble of upgrading the computer by consumer can be eliminated.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: April 29, 2003
    Assignee: VIA Technologies, Inc.
    Inventors: Chia-Hsing Yu, Nai-Shung Chang
  • Patent number: 6554195
    Abstract: A dual processor adapter card with a plurality of electrical pins for inserting into a processor slot on a mainboard by which the adapter card is electrically coupled to the mainboard. There is a first and a second processor socket on the adapter card for carrying a first and a second processor respectively. The first and the second processor socket each has a plurality of corresponding pins, a portion of the pins of the first and the second processor socket corresponds to a portion of the electrical pins. Corresponding pins are coupled together. Furthermore, each of the pins that act as a terminal lead in the first and the second processor socket is connected to a pull-up resistor, and the pull-up resistor is connected to a terminal voltage. In addition, a zero-delay buffer for synchronizing clock pulse signals and a voltage regulator for regulating a power voltage into a suitable working voltage are mounted on the adapter card and coupled to the first and the second processor socket respectively.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: April 29, 2003
    Assignee: Via Technologies, Inc.
    Inventors: Nai-Shung Chang, Lie-Wen Chen, Ching-Fu Chuang, Chia-Hsing Yu
  • Publication number: 20030065915
    Abstract: A method for initializing a computer system employs BIOS to set up a temporary storage area and a temporary setting control flag. When the user alters the configuration settings of the computer system, BIOS saves the new configuration settings into the temporary storage area as temporary configuration settings and sets the temporary setting control flag. When the computer system reboots, BIOS first unsets the temporary setting control flag and initializes the computer system according to the temporary configuration settings in the temporary storage area. If BIOS can successfully initialize the computer system with the temporary configuration settings, the CMOS RAM will be updated with the temporary configuration settings. If BIOS can not successfully initialize the computer system with the temporary configuration settings, in the later initialization of the computer system the BIOS will initialize the computer system in accordance with the configuration settings originally stored in the CMOS RAM.
    Type: Application
    Filed: April 23, 2002
    Publication date: April 3, 2003
    Inventors: Chia-Hsing Yu, Nai-Shung Chang, Ming-Hung Chen, Tsung-Yi Lin
  • Publication number: 20030042566
    Abstract: This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball.
    Type: Application
    Filed: June 14, 2002
    Publication date: March 6, 2003
    Inventors: Nai-Shung Chang, Shu-Hui Chen, Tsai-Sheng Chen, Chia-Hsing Yu
  • Publication number: 20030043143
    Abstract: An accelerated graphic port (AGP) system uses several control signals to allow an AGP graphic card to enter into negotiation with a motherboard. These control signals can drive the motherboard to provide AGP operating voltage (VCCQ) and providing a first reference voltage for the motherboard according to the AGP operating voltage. On the other hand, the motherboard will provide a second reference voltage to the AGP graphic card according to the determination of whether or not the AGP graphic card is an AGP8X card. Therefore the universal AGP connector of the present invention can enable all kinds of AGP graphic cards to be coupled to the motherboard, and can prompt the motherboard to meet with all the AGP system specifications and support all kinds of AGP graphic cards.
    Type: Application
    Filed: April 23, 2002
    Publication date: March 6, 2003
    Inventor: Chia-Hsing Yu
  • Publication number: 20020188874
    Abstract: A power controller for a computer system capable of supporting multiple processor types. The power controller receives a voltage identification signal from the microprocessor and a microprocessor selection signal from a motherboard to provide a correct voltage specification signal and terminal voltage to the microprocessor. The invention also provides voltage specification signals and terminal voltages to the motherboard of a computer system that can support a multiple of processor types.
    Type: Application
    Filed: October 22, 2001
    Publication date: December 12, 2002
    Inventors: Chia-Hsing Yu, Nai-Shung Chang
  • Publication number: 20020180507
    Abstract: A resistor network which utilizes modulating signals to modulate the resistance value of the individual resistive elements thereof. The resistor network includes a plurality of input terminals and output terminals, and a resistive element and a first switch connected in series with the resistive element is provided between each of the input terminals and output terminals. Each resistive elements includes a plurality of resistors connected in parallel, and a plurality of second switches each of which is connected with a corresponding one of the resistors. An equivalent resistance value of the resistive element is obtained between the input terminal and the output terminal by controlling the on/off states of the second switches through the modulating signals to determine which resistors can be selectively connected with the input terminal and the output terminal.
    Type: Application
    Filed: April 30, 2002
    Publication date: December 5, 2002
    Applicant: VIA Technologies, Inc.
    Inventors: Chia-Hsing Yu, Ta-Hsiu Huang
  • Publication number: 20020169916
    Abstract: According to the claimed invention, the computer system has a central processing unit, a north bridge electrically connected to the central processing unit, memory electrically connected to the north bridge, and a south bridge electrically connected to the north bridge, the south bridge having a general purpose serial input/output port. The computer also includes at least one peripheral device electrically connected to the south bridge and an interfacing circuit for providing a plurality of extended general purpose input/output ports, the interfacing circuit having a connection end electrically connected to the general purpose serial input/output port. When inputting a data signal from a general purpose input/output (GPIO) port, the data signal is transmitted to the general purpose serial input/output port through the connection end of the interfacing circuit.
    Type: Application
    Filed: April 24, 2002
    Publication date: November 14, 2002
    Inventors: Chia-Hsing Yu, Hsuan-I Wang, Chi-Hsing Lin
  • Publication number: 20020144166
    Abstract: A motherboard with reduced power consumption is disclosed. The motherboard has a memory module slot, a DDR termination array, and a control chip. The DDR termination array couples to the memory module slot and provides a termination resistor that has one terminal coupled to a voltage source. The control chip provides a control signal. When the motherboard enters a power saving mode or before the memory module being inserted in the memory module slot, the control signal gives an indication to the DDR termination array for cutting off the connection between the termination resistor and the memory module slot. A switch and several termination resistors may substitute the DDR termination array as requirements. The control chip provides the control signal to open the switch and therefore cuts off the connections between termination resistors and the voltage source to achieve the power-conserving purpose.
    Type: Application
    Filed: December 4, 2001
    Publication date: October 3, 2002
    Inventors: Nai-Shung Chang, Chia-Hsing Yu, Chia-Hsin Chen
  • Publication number: 20020099925
    Abstract: An apparatus and a method for supporting multi-processors and a motherboard using the same are provided. The apparatus receives the pins Z36 and AK36 of the Socket-370 central processing unit to determine which type the Socket-370 central processing unit is. According to the suspend status input signal transmitted from the south bridge of the motherboard, the determined result is latched, and some appropriate circuits are coupled to the Socket-370 central processing unit via a switch circuit. Meanwhile, the suspend status input signal is delayed and used to cut off the connection between the Socket-370 central processing unit and the apparatus. The delayed suspend status input signal is further delayed and then sent to an ATX power supply to activate the whole system.
    Type: Application
    Filed: October 22, 2001
    Publication date: July 25, 2002
    Inventors: Nai-Shung Chang, Chia-Hsing Yu
  • Publication number: 20020073346
    Abstract: An integrated circuit includes voltage identification (VID) logic and frequency identification logic (FID) for a CPU, as well as power good circuitry for indicating the suitability of electrical power supplies. A VID output signal to control a core voltage provided to the CPU is generated according to an input VID signal provided by the CPU, a sleep state signal, and a CPU mobility-type signal. FID, VID and power detection logic all level shift signals as required for external devices. A programmable table enables overriding of output FID and VID values.
    Type: Application
    Filed: December 5, 2001
    Publication date: June 13, 2002
    Inventors: Chia-Hsing Yu, Nai-Shung Chang
  • Publication number: 20020039045
    Abstract: An apparatus for providing both supports including synchronous dynamic random access memory module and the double data rate dynamic random access memory module is provided. A motherboard can support standard synchronous dynamic random access memory and dual data rate dynamic random access memory by using the disable and enable functions of the terminator. The invention reduces manufacturing production waste due to complex fabrication process of memory module. In addition, the trouble of upgrading the computer by consumer can be eliminated.
    Type: Application
    Filed: August 14, 2001
    Publication date: April 4, 2002
    Inventors: Chia-Hsing Yu, Nai-Shung Chang