Abstract: The graphics display architecture provided by the present invention comprises an AGP slot, a PCIE slot, and a control chip set. The control chip set comprises a plurality of multi-defined pins, which are electrically coupled to the first pins of the AGP slot and the second pins of the PCIE slot simultaneously. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with AGP interface specification, the multi-defined pins serve to send/receive the signal complied with AGP interface specification. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with the Gfx interface, the multi-defined pins serve to send/receive the signal complied with the Gfx interface. When the second graphics adapter is plugged in the PCIE slot, the multi-defined pins serve to send/receive the signal complied wit the PCIE interface specification.

Abstract: A method for determining an operating voltage of floating point error detection is implemented by a central processing unit (CPU) and a south bridge chipset. The CPU has a first output port connected to a test port of the south bridge. The test port is used to determine an operating voltage of the CPU. If the operating voltage of the CPU is greater than a predetermined value, the first output port is floating. If the operating voltage of the CPU is smaller than the predetermined value, the first output port is grounded. The method includes using a power supply and a resistor to provide a bias voltage and for measuring a voltage of the test port to determine the operating voltage of the CPU.

Abstract: Multi-function chipset and related design/manufacturing method for realizing different kinds of chipsets respectively supporting accelerated graphic port (AGP) bus and peripheral component interconnect extended (PCI-X) bus. The integrated circuit of the chipset includes both the AGP and PCI-X bus controllers, which share a common I/O pad configuration, and the chipset is selected to be an AGP-supported chipset or a PCI-X supported chipset by pin strapping. Also, the chipset can be packaged with different wire bonding configurations to alternatively realize chipsets supporting AGP bus or PCI-X bus.

Abstract: A control chip supporting a plurality of buses and control chip set thereof is provided. A control chip supporting a plurality of buses chooses a type of bus for complying with another control chip based on the bus type thereby, wherein a device and a driving circuit are included. The device generates required controlling timings based on selection pins. The driving circuit enables required transmitting direction of pins based on selection pins per se.

Abstract: An adaptive device for a memory simulator is capable of connecting a transmission interface of a memory simulator to a memory socket of a motherboard, in which the transmission interface is not compatible to the memory socket. The adaptive device includes first and second connectors respectively suitable for connecting with a first read-only memory socket and a second read-only memory socket. If the first connector is connected with the first read-only memory socket, a controller of the adaptive device performs a first access mode to access the system code and passes it to the first read-only memory socket via the first connector. If the second connector is connected with the second read-only memory socket, the controller performs a second access mode to access the system code and passes it to the second read-only memory socket via the second connector for the motherboard to execute it.

Abstract: A memory emulating apparatus and its method are proposed to emulate a read-only memory (ROM) of a motherboard. The motherboard has a first or a second ROM socket. The present invention includes a first and second connectors for connecting with the first and the second ROM socket respectively, a rewritable memory for storing a system code and a controller connected with the first and second connectors and the rewritable memory. If the first connector is connected to the first ROM socket, the controller enters a first access mode to access the system code and passes it to the first ROM socket via the first connector. Otherwise, if the second connector is connected to the second ROM socket, the controller enters a second access mode to access the system code and passes it to the second ROM socket via the second connector for the motherboard to check.

Abstract: A motherboard with reduced power consumption is disclosed. The motherboard has a memory module slot, a DDR termination array, and a control chip. The DDR termination array couples to the memory module slot and provides a termination resistor that has one terminal coupled to a voltage source. The control chip provides a control signal. When the motherboard enters a power saving mode or before the memory module being inserted in the memory module slot, the control signal gives an indication to the DDR termination array for cutting off the connection between the termination resistor and the memory module slot. A switch and several termination resistors may substitute the DDR termination array as requirements. The control chip provides the control signal to open the switch and therefore cuts off the connections between termination resistors and the voltage source to achieve the power-conserving purpose.

Abstract: An apparatus and a method for supporting multi-processors and a motherboard using the same are provided. The apparatus receives the pins Z36 and AK36 of the Socket-370 central processing unit to determine which type the Socket-370 central processing unit is. According to the suspend status input signal transmitted from the south bridge of the motherboard, the determined result is latched, and some appropriate circuits are coupled to the Socket-370 central processing unit via a switch circuit. Meanwhile, the suspend status input signal is delayed and used to cut off the connection between the Socket-370 central processing unit and the apparatus. The delayed suspend status input signal is further delayed and then sent to an ATX power supply to activate the whole system.

Abstract: This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball. In addition, in the embodiment of the main bridge chip substrate, decoupling capacitors can be disposed at four corners of the power ring or underneath the bonding wires, or can be packaged inside the molding compound.

Abstract: According to the claimed invention, the computer system has a central processing unit, a north bridge electrically connected to the central processing unit, memory electrically connected to the north bridge, and a south bridge electrically connected to the north bridge, the south bridge having a general purpose serial input/output port. The computer also includes at least one peripheral device electrically connected to the south bridge and an interfacing circuit for providing a plurality of extended general purpose input/output ports, the interfacing circuit having a connection end electrically connected to the general purpose serial input/output port. When inputting a data signal from a general purpose input/output (GPIO) port, the data signal is transmitted to the general purpose serial input/output port through the connection end of the interfacing circuit.

Abstract: This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball. In addition, in the embodiment of the main bridge chip substrate, decoupling capacitors can be disposed at four corners of the power ring or underneath the bonding wires, or can be packaged inside the molding compound.

Abstract: A power controller for a computer system capable of supporting multiple processor types. The power controller receives a voltage identification signal from the microprocessor and a microprocessor selection signal from a motherboard to provide a correct voltage specification signal and terminal voltage to the microprocessor. The invention also provides voltage specification signals and terminal voltages to the motherboard of a computer system that can support a multiple of processor types.

Abstract: The graphics display architecture provided by the present invention comprises an AGP slot, a PCIE slot, and a control chip set. The control chip set comprises a plurality of multi-defined pins, which are electrically coupled to the first pins of the AGP slot and the second pins of the PCIE slot simultaneously. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with AGP interface specification, the multi-defined pins serve to send/receive the signal complied with AGP interface specification. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with the Gfx interface, the multi-defined pins serve to send/receive the signal complied with the Gfx interface. When the second graphics adapter is plugged in the PCIE slot, the multi-defined pins serve to send/receive the signal complied wit the PCIE interface specification.

Abstract: A control chip supporting a plurality of buses and control chip set thereof is provided. A control chip supporting a plurality of buses chooses a type of bus for complying with another control chip based on the bus type thereby, wherein a device and a driving circuit are included. The device generates required controlling timings based on selection pins. The driving circuit enables required transmitting direction of pins based on selection pins per se.

Abstract: An integrated circuit includes voltage identification (VID) logic and frequency identification logic (FID) for a CPU, as well as power good circuitry for indicating the suitability of electrical power supplies. A VID output signal to control a core voltage provided to the CPU is generated according to an input VID signal provided by the CPU, a sleep state signal, and a CPU mobility-type signal. FID, VID and power detection logic all level shift signals as required for external devices. A programmable table enables overriding of output FID and VID values.

Abstract: An accelerated graphic port (AGP) system uses several control signals to allow an AGP graphic card to enter into negotiation with a motherboard. These control signals can drive the motherboard to provide AGP operating voltage (VCCQ) and providing a first reference voltage for the motherboard according to the AGP operating voltage. On the other hand, the motherboard will provide a second reference voltage to the AGP graphic card according to the determination of whether or not the AGP graphic card is an AGP8X card. Therefore the universal AGP connector of the present invention can enable all kinds of AGP graphic cards to be coupled to the motherboard, and can prompt the motherboard to meet with all the AGP system specifications and support all kinds of AGP graphic cards.

Abstract: An additional data transmission channel is provided between the north bridge chip and the system memory when the graphic accelerator is integrated into the north bridge chip. The additional data transmission channel can be similar to the existent data transmission channel between the north bridge chip and the system memory for providing extensive data transmission bandwidth. Alternatively, the additional data transmission channel can be specific to the communication between the graphic accelerator in the north bridge chip and the frame buffer in the system memory.

Abstract: A control chipset having dual-definition data pins capable of reducing circuit layout to memory module slots. Using dual-definition data pins of the control chipset and multiplexing/de-multiplexing devices, the control chipset is able to sense the particular type of memory modules plugged into memory slots automatically and hence assigning the function to each data pin accordingly. Consequently, circuit layout from the control chipset to the data pins of far off memory slots is simplified and overall circuit length is greatly reduced.

Abstract: An enhanced Printed Circuit Board (PCB) and stacked substrate structure. In one embodiment, each middle layer is coupled between two ground layers except for the top signal layer and the bottom solder layer. In another embodiment, the top signal layer and the bottom solder layer are respectively coupled between two ground layers, so all signal layers are implemented in the stacked substrate structure and any internal signal layer is coupled between two ground layers. Thus, all signals can refer to adjacent ground layers and achieve better signal quality. Also, each capacitance structure formed by a signal layer and a ground layer increases the operating speed of the entire circuit.

Abstract: A method for determining an operating voltage of floating point error detection is implemented by a central processing unit (CPU) and a south bridge chipset. The CPU has a first output port connected to a test port of the south bridge. The test port is used to determine an operating voltage of the CPU. If the operating voltage of the CPU is greater than a predetermined value, the first output port is floating. If the operating voltage of the CPU is smaller than the predetermined value, the first output port is grounded. The method includes using a power supply and a resistor to provide a bias voltage and for measuring a voltage of the test port to determine the operating voltage of the CPU.