Abstract: A package structure and a method of forming the same are provided. The package structure includes an integrated circuit die and a redistribution structure bonded to the integrated circuit die. The redistribution structure includes a first insulating layer, a second insulating layer interposed between the first insulating layer and the integrated circuit die, and a first metallization pattern in the first insulating layer and the second insulating layer. The first metallization pattern includes a first conductive line and a first conductive via coupled to the first conductive line. The first conductive line is in the second insulating layer. The first conductive via is in the first insulating layer. The first conductive line includes a first conductive pad coupled to the first conductive via, a second conductive pad, and a curved portion connecting the first conductive pad to the second conductive pad.

Abstract: A package structure and a method of forming the same are provided. The package structure includes an integrated circuit die and a redistribution structure bonded to the integrated circuit die. The redistribution structure includes a first insulating layer, a second insulating layer interposed between the first insulating layer and the integrated circuit die, and a first metallization pattern in the first insulating layer and the second insulating layer. The first metallization pattern includes a first conductive line and a first conductive via coupled to the first conductive line. The first conductive line is in the second insulating layer. The first conductive via is in the first insulating layer. The first conductive line includes a first conductive pad coupled to the first conductive via, a second conductive pad, and a curved portion connecting the first conductive pad to the second conductive pad.

Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.

Abstract: A method for specifying layout of subpictures in video pictures is provided. A video decoder receives data from a bitstream to be decoded as a current picture of a video. For a current subpicture of a set of subpictures of the current picture, the video decoder determines a position of the current subpicture based on a width and a height of the current picture and a previously determined width and height of a particular subpicture in the set of subpictures. The video decoder reconstructs the current picture and the current subpicture based on the determined position.

Abstract: An electronic device, including a metal back cover, a ground radiator, a third radiator, and a metal frame including a first cutting opening, a second cutting opening, a first radiator located between the first cutting opening and the second cutting opening, and a second radiator located beside the second cutting opening and separated from the first radiator by the second cutting opening, is provided. An end of a first slot formed between the metal back cover and a first part of the first radiator is communicated with the first cutting opening, and a second slot formed between the metal back cover and a second part of the first radiator and between the metal back cover and the second radiator is communicated with the second cutting opening. The ground radiator connects the metal back cover and the first radiator and separates the first slot from the second slot.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: Method and apparatus for template matching with a determined area are disclosed. According to this method, a current template comprising current neighbouring pixels on an above side of the current block, on a left side of the current block, or a combination thereof for a current block is received. An area in a reference picture is then determined, where the reference picture corresponds to a previously coded picture. A matching result between a restricted reference template of a reference block and the current template is then determined, wherein the restricted reference template is generating by using only neighbouring reference pixels of a reference template inside the determined area, the reference template has a same shape as the current template, and a location of the reference template is determined according to a target motion vector (MV) from the current template.

Abstract: A method and apparatus for video coding system that utilizes low-latency template-matching motion-vector refinement are disclosed. According to this method, input data associated with a current block of a video unit in a current picture are received. Motion compensation is then applied to the current block according to an initial motion vector (MV) to obtain initial motion-compensated predictors of the current. After applying the motion compensation to the current block, template-matching MV refinement is applied to the current block to obtain a refined MV for the current block. The current block is then encoded or decoded using information including the refined MV. The method may further comprise determining gradient values of the initial motion-compensated predictors. The initial motion-compensated predictors can be adjusted by taking into consideration of the gradient values and/or MV difference between the refined and initial MVs.

Abstract: A keyboard for use with an electronic device including an electronic processor. The keyboard includes a printed circuit board that is configured to communicate with the electronic processor of the electronic device, a first plurality of physical keys, and a second plurality of dedicated physical keys. Each of the first plurality of physical keys is movable between an unactuated position and an actuated position. When in the actuated position, each of the first plurality of physical keys is configured to generate a first signal that inserts a character on the electronic device. Each of the second plurality of dedicated physical keys is movable between an unactuated position and an actuated position. When in the actuated position, each of the second plurality of dedicated physical keys is configured to generate a second signal that performs a function in a teleconferencing application running on the electronic device.

Abstract: A method and apparatus for video coding system that utilizes low-latency template-matching motion-vector refinement are disclosed. According to this method, a current template for a current block is determined, where the current template includes an inside current template including inside prediction samples or inside partially reconstructed samples inside the current block. The inside partially reconstructed samples are derived by adding a DC value of the current block to the inside prediction samples. Corresponding candidate reference templates associated with the current block are determined at a set of candidate locations. A location of a target reference template among the candidate reference templates that achieves a best match between the current template and the candidate reference templates is determined. An initial motion vector (MV) is then refined according to the location of the target reference template.

Abstract: A method and apparatus for video coding system that utilizes low-latency template-matching motion-vector refinement are disclosed. According to this method, a current template for the current block is determined, where at least one of current above template and current left template is removed or is located away from a respective above edge or a respective left edge of the current block and the current template is generated using reconstructed samples. Candidate reference templates, corresponding to the current template at respective candidate locations, associated with the current block at a set of candidate locations in a reference picture are determined. A location of a target reference template among the candidate reference templates is determined, where the target reference template achieves a best match with the current template. A refined motion vector (MV) is determined by refining an initial MV according to the location of the target reference template.

Abstract: A video coding system that uses template matching (TM) to improve signaling of coding modes is provided. The system receives data to be encoded or decoded as a current block of a current picture of a video. The system identifies a set of pixels neighboring the current block as a current template. The system identifies a reference template of each candidate coding mode in a plurality of candidate coding modes. The system computes a template matching (TM) cost for each candidate coding mode based on matching the current template with the reference template of the candidate coding mode. The system selects a candidate coding mode from the plurality of candidate coding modes based on the computed TM costs. The system reconstructs the current block or encoding the current block into a bitstream by using selected candidate coding mode.

Abstract: A communication device includes a first ground element, a second ground element, a third ground element, a first signaling conductor, a second signaling conductor, a resonant circuit, and a dielectric substrate. The first signaling conductor is disposed between the first ground element and the second ground element. The second signaling conductor is disposed between the second ground element and the third ground element. The first signaling conductor is coupled through the resonant circuit to the first ground element. The dielectric substrate has a first surface and a second surface opposite to each other. The first ground element, the second ground element, the third ground element, the first signaling conductor, and the second signaling conductor are disposed on the first surface of the dielectric substrate. The resonant circuit is configured to increase the isolation between the first signaling conductor and the second signaling conductor in a target frequency band.

Abstract: A video coding system generating candidates for Merge Mode with Motion Vector Difference (MMVD) with reduced resource usage is provided. The system receives data to be encoded or decoded as a current block of a current picture of a video. The system identifies multiple MMVD candidates for different offset positions based on a merge candidate of the current block. The system generates reference samples for the identified MMVD candidates. The system reconstructs the current block or encodes the current block into a bitstream by using the generated reference samples. The system processes the MMVD candidates in separate groups: a first group of vertical MMVD candidates and a second group of horizontal MMVD candidates. The system generates the reference samples for the identified MMVD candidates by applying a vertical filter to source reference samples of horizontal MMVD candidates and then applying a horizontal filter to outputs of the vertical filter.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming a fin-shaped structure on the substrate, forming a gate structure on the fin-shaped structure, removing the fin-shaped structure to form a recess, forming a first epitaxial layer in the recess adjacent to the gate structure, and then forming a second epitaxial layer on the first epitaxial layer. Preferably, the semiconductor device further includes a first protrusion on one side of the first epitaxial layer and a second protrusion on another side of the first epitaxial layer.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a circuit assembly. The movable assembly is configured to connect an optical element, the movable assembly is movable relative to the fixed assembly, and the optical element has an optical axis. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The circuit assembly includes a plurality of circuits and is affixed to the fixed assembly.

Abstract: A lighting touchpad is provided. The lighting touchpad includes a substrate, a plurality of first electrodes, a plurality of second electrodes, a plurality of bonding pads and a plurality of lighting devices. The plurality of first electrodes, the plurality of second electrodes and the plurality of bonding pads are arranged on the substrate, and the first electrodes, the second electrodes, and the bonding pads are alternately arranged in a sensing area without overlapping with one another. The pluralities of lighting devices are connected to a part of the bonding pads.

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.