Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, and a barrier layer. The first conductive feature is disposed on the first dielectric layer, the second dielectric layer is disposed on the first dielectric layer and surrounds the sidewalls of the first conductive feature, the barrier layer is disposed between the first dielectric layer and the second dielectric layer and between the sidewalls of the first conductive feature and the second dielectric layer.

Abstract: The semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first dielectric layer, a first metal layer, a second metal layer, a first etching stop layer, a second etching stop layer, a second dielectric layer, a first via and a second via. The first metal layer and the second metal are embedded in the first dielectric layer. The first etching stop layer is disposed on the first dielectric layer. The second etching stop layer is disposed on the first etching stop layer. The second dielectric layer is disposed on the second etching stop layer. The first via and the second via are embedded in the second dielectric layer. A width of the second etching stop layer is smaller a width of the first etching stop layer.

Abstract: A light source module is provided, including: a light board, including a substrate, and a plurality of light-emitting elements arranged at intervals on the substrate; and a separator, located above the substrate, and including a plurality of first ribs, where the plurality of first ribs is cross-connected to form a plurality of interval spaces, to accommodate the light-emitting elements, the first rib forming the interval space has an inner wall, a part of the inner wall in a direction closer to the substrate tapers in a direction far away from the interval space, the inner wall has a first distance farther away from the substrate in a Z-axis direction and has a second distance closer to the substrate, and a projection relationship between the second distance and the first distance onto an XY plane is that the second distance is greater than the first distance.

Abstract: A micro-electro-mechanical system (MEMS) microphone is provided. The MEMS microphone includes a substrate, a backplate, an insulating layer, and a diaphragm. The substrate has an opening portion. The backplate is disposed on a side of the substrate, with protrusions protruding toward the substrate. The diaphragm is movably disposed between the substrate and the backplate and spaced apart from the backplate by a spacing distance. The protrusions are configured to limit the deformation of the diaphragm when air flows through the opening portion.

Abstract: A method for fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer; depositing a second dielectric layer over the first dielectric layer; etching a trench opening in the second dielectric layer, wherein the trench opening exposes a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer, the first sidewall of the second dielectric layer extends substantially along a first direction, and the second sidewall of the second dielectric layer extends substantially along a second direction different from the first direction in a top view; forming a via etch stop layer on the first sidewall of the second dielectric layer, wherein the second sidewall of the second dielectric layer is free from coverage by the via etch stop layer; forming a conductive line in the trench opening; and forming a conductive via over the conductive line.

Abstract: An image signal amplifying circuit comprising an amplifier and a gain control circuit. The amplifier respectively amplifies a first image signal and a second image signal, which are generated by a pixel array of an image sensor, by a first analog gain and a second analog gain, wherein each one of pixel circuits of the pixel array comprises a first capacitor for generating the first image signal and a second capacitor for generating the second image signal, wherein a charge storage capacity of the first capacitor is smaller than a charge storage capacity of the second capacitor. The gain control circuit selectively adjusts the first analog gain or the second analog gain. Each one of the pixel circuits has a first conversion gain corresponding to the first capacitor and a second conversion gain corresponding to the second capacitor.

Abstract: A semiconductor device including a circuit substrate, a chip package, and a stiffener ring is provided. The chip package is disposed on and electrically connected to the circuit substrate, the chip package includes a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides. The stiffener ring is disposed on the circuit substrate, the stiffener ring includes first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides. The first stiffener portions are connected to the second stiffener portions, and the second stiffener portions is mechanically weaker than the first stiffener portions. A semiconductor device including stiffener lids is also provided.

Abstract: Video encoding or decoding methods and apparatuses include receiving input data associated with a current block in a current picture, determining a preload region in a reference picture shared by two or more coding configurations of affine prediction or motion compensation or by two or more affine refinement iterations, loading reference samples in the preload region, generating predictors for the current block, and encoding or decoding the current block according to the predictors. The predictors associated with the affine refinement iterations or coding configurations are generated based on some of the reference samples in the preload region.

Abstract: Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of semiconductor layers. The semiconductor layers are stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. A third conductive feature is formed over the first epitaxy region and within the oxide diffusion region. A fourth conductive feature is formed over the second epitaxy region and within the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features.

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

Abstract: A polypropylene-based outsole material, which includes, based on 100 wt % of the polypropylene-based outsole material, a polypropylene homopolymer present in an amount ranging from 5 wt % to 25 wt %, a thermoplastic polypropylene copolymer present in an amount ranging from 70 wt % to 87 wt %, and a modifier present in an amount greater than 0 wt % and not greater than 10 wt %. The modifier is a maleic anhydride-grafted polyolefin elastomer. A footwear sole structure including an outsole made of the polypropylene-based outsole material, and a footwear article including the footwear sole structure are also provided.

Abstract: A capacitive touchpad is provided, which includes a substrate module, a plurality of sensing electrodes, a plurality of driving electrodes and a plurality of light-emitting diode (LED) dies. The plurality of sensing electrodes and the plurality of driving electrodes form a touch sensing region of the capacitive touchpad, and the touch sensing region is divided into a plurality of sensing units having same areas. Each of the LED dies is arranged in two adjacent ones of the plurality of sensing units, and a position of each of the LED dies corresponds to one of the plurality of driving electrodes, and the LED dies are electrically isolated from the plurality of sensing electrodes and the plurality of driving electrodes.

Abstract: A method and apparatus for video coding are disclosed. According to the method, a set of MC (Motion Compensation) candidates with each MC candidate comprising predicted samples for coding boundary pixels of the current block are determined. The set of MC candidates comprises a first candidate, and wherein the first candidate corresponds to a weighted sum of first predicted pixels generated according to first motion information of the current block and second predicted pixels generated according to second motion information of a neighbouring boundary block of the current block. Boundary matching costs associated with the set of MC candidates are determined respectively. A final candidate is determined from the set of MC candidates based on the boundary matching costs. The current block is encoded or decoded using the final candidate.

Abstract: A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, semiconductor dies over the package substrate, and an underfill element over the package substrate and surrounding the semiconductor dies. A portion of the underfill element is located between the semiconductor dies. The semiconductor die package also includes lid structures respectively attached to the top surfaces of the semiconductor dies. In plan view, each lid structure is located within the periphery of the top surface of the corresponding semiconductor die. Each lid structure is disconnected from other lid structures, and a gap is formed between adjacent lid structures and located over the portion of the underfill element.

Abstract: A card edge connector includes: a connector base having a card slot and plural terminals; a latch located at one end of the connector base for locking a card; and a releasing member. The releasing member includes two levers and a moving member, the levers are connected with the connector base in a pivoting manner, a first end of the lever is connected with the latch and an opposite second end of the lever is coupled to the moving member, wherein when the card is inserted into the slot and presses against the moving member downwards, the moving member drives the second ends of the levers to move downward, resulting in the first ends moving upwards to push the latch to lock with the card, and when the card is pulled out the moving member resets and drives the levers to release the latch from the card.

Abstract: A computer-assisted needle insertion method is provided. The computer-assisted needle insertion method includes the following steps. A first machine learning model and a second machine learning model are obtained. A computed tomography image and a needle insertion path are obtained, a suggested needle insertion path is generated according to the first machine learning model, the computed tomography image, and the needle insertion path, and the needle is instructed to approach a needle insertion point on a skin of a target. The needle insertion point is located on the suggested needle insertion path. A breath signal of the target is obtained, and whether a future breath state of the target is normal is estimated according to the second machine learning model and the breath signal. A suggested needle insertion period is output according to the breath signal in response to determining that the future breath state is normal.

Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

Abstract: A semiconductor device includes a substrate, a stiffener ring over the substrate, and an adhesive ring between the substrate and the stiffener ring. The adhesive ring includes a first part, a second part and a third part disposed between the first part and the second part. The first part and the second part have a first thickness, and the third part has a second thickness greater than the first thickness. The third part of the adhesive ring is covered by the stiffener ring.

Abstract: The disclosure provides an electronic device. The electronic device includes a substrate, a transistor, and a variable capacitor. The transistor is disposed on the substrate. The variable capacitor is disposed on the substrate and adjacent to the transistor. A material of the transistor and a material of the variable capacitor both a include a III-V semiconductor material. The electronic device of an embodiment of the disclosure may simplify manufacturing process, reduce costs, or reduce dimensions.