Patents by Inventor Chia Hsu
Chia Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250112087Abstract: A method for fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer; depositing a second dielectric layer over the first dielectric layer; etching a trench opening in the second dielectric layer, wherein the trench opening exposes a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer, the first sidewall of the second dielectric layer extends substantially along a first direction, and the second sidewall of the second dielectric layer extends substantially along a second direction different from the first direction in a top view; forming a via etch stop layer on the first sidewall of the second dielectric layer, wherein the second sidewall of the second dielectric layer is free from coverage by the via etch stop layer; forming a conductive line in the trench opening; and forming a conductive via over the conductive line.Type: ApplicationFiled: October 3, 2023Publication date: April 3, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hwei-Jay CHU, Hsi-Wen TIEN, Wei-Hao LIAO, Yu-Teng DAI, Hsin-Chieh YAO, Tzu-Hui WEI, Chih Wei LU, Chan-Yu LIAO, Li-Ling SU, Chia-Wei SU, Yung-Hsu WU, Hsin-Ping CHEN
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Patent number: 12267597Abstract: An image signal amplifying circuit comprising an amplifier and a gain control circuit. The amplifier respectively amplifies a first image signal and a second image signal, which are generated by a pixel array of an image sensor, by a first analog gain and a second analog gain, wherein each one of pixel circuits of the pixel array comprises a first capacitor for generating the first image signal and a second capacitor for generating the second image signal, wherein a charge storage capacity of the first capacitor is smaller than a charge storage capacity of the second capacitor. The gain control circuit selectively adjusts the first analog gain or the second analog gain. Each one of the pixel circuits has a first conversion gain corresponding to the first capacitor and a second conversion gain corresponding to the second capacitor.Type: GrantFiled: March 7, 2023Date of Patent: April 1, 2025Assignee: MEDIATEK INC.Inventors: Chi-Cheng Ju, Hsun-Chia Hsu, I-Hsien Lee
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Publication number: 20250105090Abstract: A semiconductor device including a circuit substrate, a chip package, and a stiffener ring is provided. The chip package is disposed on and electrically connected to the circuit substrate, the chip package includes a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides. The stiffener ring is disposed on the circuit substrate, the stiffener ring includes first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides. The first stiffener portions are connected to the second stiffener portions, and the second stiffener portions is mechanically weaker than the first stiffener portions. A semiconductor device including stiffener lids is also provided.Type: ApplicationFiled: December 10, 2024Publication date: March 27, 2025Inventors: Chien-Chia Chiu, Li-Han Hsu
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Patent number: 12255201Abstract: Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of semiconductor layers. The semiconductor layers are stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. A third conductive feature is formed over the first epitaxy region and within the oxide diffusion region. A fourth conductive feature is formed over the second epitaxy region and within the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features.Type: GrantFiled: November 28, 2023Date of Patent: March 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Chia Hsu, Tung-Heng Hsieh, Yung-Feng Chang, Bao-Ru Young, Jam-Wem Lee, Chih-Hung Wang
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Patent number: 12256094Abstract: Video encoding or decoding methods and apparatuses include receiving input data associated with a current block in a current picture, determining a preload region in a reference picture shared by two or more coding configurations of affine prediction or motion compensation or by two or more affine refinement iterations, loading reference samples in the preload region, generating predictors for the current block, and encoding or decoding the current block according to the predictors. The predictors associated with the affine refinement iterations or coding configurations are generated based on some of the reference samples in the preload region.Type: GrantFiled: May 4, 2022Date of Patent: March 18, 2025Assignee: MEDIATEK INC.Inventors: Chih-Hsuan Lo, Tzu-Der Chuang, Ching-Yeh Chen, Chun-Chia Chen, Chih-Wei Hsu, Yu-Wen Huang
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Publication number: 20250087550Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.Type: ApplicationFiled: November 22, 2024Publication date: March 13, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih Lai, Chien-Chia Chiu, Chen-Hua Yu, Der-Chyang Yeh, Cheng-Hsien Hsieh, Li-Han Hsu, Tsung-Shu Lin, Wei-Cheng Wu, Yu-Chen Hsu
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Publication number: 20250074036Abstract: A polypropylene-based outsole material, which includes, based on 100 wt % of the polypropylene-based outsole material, a polypropylene homopolymer present in an amount ranging from 5 wt % to 25 wt %, a thermoplastic polypropylene copolymer present in an amount ranging from 70 wt % to 87 wt %, and a modifier present in an amount greater than 0 wt % and not greater than 10 wt %. The modifier is a maleic anhydride-grafted polyolefin elastomer. A footwear sole structure including an outsole made of the polypropylene-based outsole material, and a footwear article including the footwear sole structure are also provided.Type: ApplicationFiled: December 22, 2023Publication date: March 6, 2025Inventors: Hung-Chia YEN, Pei-Neng HSU
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Publication number: 20250068286Abstract: A capacitive touchpad is provided, which includes a substrate module, a plurality of sensing electrodes, a plurality of driving electrodes and a plurality of light-emitting diode (LED) dies. The plurality of sensing electrodes and the plurality of driving electrodes form a touch sensing region of the capacitive touchpad, and the touch sensing region is divided into a plurality of sensing units having same areas. Each of the LED dies is arranged in two adjacent ones of the plurality of sensing units, and a position of each of the LED dies corresponds to one of the plurality of driving electrodes, and the LED dies are electrically isolated from the plurality of sensing electrodes and the plurality of driving electrodes.Type: ApplicationFiled: November 7, 2024Publication date: February 27, 2025Inventors: CHE-CHIA HSU, CHI-CHIEH LIAO, YU-HAN CHEN
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Publication number: 20250064478Abstract: A computer-assisted needle insertion method is provided. The computer-assisted needle insertion method includes the following steps. A first machine learning model and a second machine learning model are obtained. A computed tomography image and a needle insertion path are obtained, a suggested needle insertion path is generated according to the first machine learning model, the computed tomography image, and the needle insertion path, and the needle is instructed to approach a needle insertion point on a skin of a target. The needle insertion point is located on the suggested needle insertion path. A breath signal of the target is obtained, and whether a future breath state of the target is normal is estimated according to the second machine learning model and the breath signal. A suggested needle insertion period is output according to the breath signal in response to determining that the future breath state is normal.Type: ApplicationFiled: November 11, 2024Publication date: February 27, 2025Applicant: Industrial Technology Research InstituteInventors: Po-An Hsu, Chih-Chi Chang, Chih-Wei Chien, Chia-Pin Li, Kun-Ta Wu, Wei-Zheng Lu
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Publication number: 20250069982Abstract: A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, semiconductor dies over the package substrate, and an underfill element over the package substrate and surrounding the semiconductor dies. A portion of the underfill element is located between the semiconductor dies. The semiconductor die package also includes lid structures respectively attached to the top surfaces of the semiconductor dies. In plan view, each lid structure is located within the periphery of the top surface of the corresponding semiconductor die. Each lid structure is disconnected from other lid structures, and a gap is formed between adjacent lid structures and located over the portion of the underfill element.Type: ApplicationFiled: November 13, 2024Publication date: February 27, 2025Inventors: Shu-Shen YEH, Che-Chia YANG, Chia-Kuei HSU, Ming-Chih YEW, Po-Yao LIN, Shin-Puu JENG
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Publication number: 20250071923Abstract: A card edge connector includes: a connector base having a card slot and plural terminals; a latch located at one end of the connector base for locking a card; and a releasing member. The releasing member includes two levers and a moving member, the levers are connected with the connector base in a pivoting manner, a first end of the lever is connected with the latch and an opposite second end of the lever is coupled to the moving member, wherein when the card is inserted into the slot and presses against the moving member downwards, the moving member drives the second ends of the levers to move downward, resulting in the first ends moving upwards to push the latch to lock with the card, and when the card is pulled out the moving member resets and drives the levers to release the latch from the card.Type: ApplicationFiled: August 19, 2024Publication date: February 27, 2025Inventors: KUO-CHUN HSU, Ming-Yi Gong, Yu-Che Huang, Wen-Lung Hsu, Po-Fu Chen, Xun Wu, Wen-Ting Yu, Chin-Chuan Wu, Wei-Chia Liao
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Publication number: 20250071260Abstract: A method and apparatus for video coding are disclosed. According to the method, a set of MC (Motion Compensation) candidates with each MC candidate comprising predicted samples for coding boundary pixels of the current block are determined. The set of MC candidates comprises a first candidate, and wherein the first candidate corresponds to a weighted sum of first predicted pixels generated according to first motion information of the current block and second predicted pixels generated according to second motion information of a neighbouring boundary block of the current block. Boundary matching costs associated with the set of MC candidates are determined respectively. A final candidate is determined from the set of MC candidates based on the boundary matching costs. The current block is encoded or decoded using the final candidate.Type: ApplicationFiled: January 10, 2023Publication date: February 27, 2025Inventors: Chun-Chia CHEN, Olena CHUBACH, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
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Patent number: 12237288Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.Type: GrantFiled: August 9, 2023Date of Patent: February 25, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou, Shu Chia Hsu, Yu-Yun Huang, Wen-Yao Chang, Yu-Jen Cheng
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Publication number: 20250063801Abstract: The disclosure provides an electronic device. The electronic device includes a substrate, a transistor, and a variable capacitor. The transistor is disposed on the substrate. The variable capacitor is disposed on the substrate and adjacent to the transistor. A material of the transistor and a material of the variable capacitor both a include a III-V semiconductor material. The electronic device of an embodiment of the disclosure may simplify manufacturing process, reduce costs, or reduce dimensions.Type: ApplicationFiled: October 31, 2024Publication date: February 20, 2025Applicant: Innolux CorporationInventors: Chin-Lung Ting, Jen-Hai Chi, Chia-Ping Tseng, Chen-Lin Yeh, Chung-Kuang Wei, Cheng-Hsu Chou
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Publication number: 20250062250Abstract: A semiconductor device includes a substrate, a stiffener ring over the substrate, and an adhesive ring between the substrate and the stiffener ring. The adhesive ring includes a first part, a second part and a third part disposed between the first part and the second part. The first part and the second part have a first thickness, and the third part has a second thickness greater than the first thickness. The third part of the adhesive ring is covered by the stiffener ring.Type: ApplicationFiled: November 6, 2024Publication date: February 20, 2025Inventors: KUAN-YU HUANG, SUNG-HUI HUANG, PAI-YUAN LI, SHU-CHIA HSU, HSIANG-FAN LEE, SZU-PO HUANG
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Publication number: 20250056008Abstract: A video coding system that uses multiple models to predict chroma samples is provided. The video coding system receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. The system constructs two or more chroma prediction models based on luma and chroma samples neighboring the current block. The system applies the two or more chroma prediction models to incoming or reconstructed luma samples of the current block to produce two or more model predictions. The system computes predicted chroma samples by combining the two or more model predictions. The system uses the predicted chroma samples to reconstruct chroma samples of the current block or to encode the current block.Type: ApplicationFiled: December 20, 2022Publication date: February 13, 2025Inventors: Yu-Ling HSIAO, Olena CHUBACH, Chun-Chia CHEN, Chia-Ming TSAI, Man-Shu CHIANG, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
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Patent number: 12223151Abstract: A circuit carrier includes a substrate, a capacitive electrode layer, a plurality of metal pads and a plurality of bridges, and a plurality of conductive pillars. The capacitive electrode layer formed on a surface of the substrate and includes a plurality of first electrodes and a plurality of second electrodes. At least two of the first electrodes are connected to each other and be arranged across a die-bonding region of the substrate for separating at least two of the second electrodes that partially protrude from the die-bonding region to respectively form extensions. The metal pads and the bridges are formed on another surface of the substrate and are located outside of the die-bonding region. Each of the bridges connects two of the metal pads, and each of the conductive pillars is embedded in the substrate and connects one of the extensions and a corresponding one of metal pads.Type: GrantFiled: April 19, 2024Date of Patent: February 11, 2025Assignee: PIXART IMAGING INC.Inventors: Che-Chia Hsu, Chun-Lin Tseng, Yu-Han Chen
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Publication number: 20250043075Abstract: A modified polyphenylene ether resin having a structure represented by [Formula 1] is provided.Type: ApplicationFiled: November 7, 2023Publication date: February 6, 2025Applicant: NAN YA PLASTICS CORPORATIONInventors: Cheng-Chung Lee, Chen Hua Wu, Jung Kai Chang, Yun-Chia Tsai, Hung-Wen Hsu
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Publication number: 20250043475Abstract: An engineered textile includes a plurality of yarn strands with a subset extending in a substantially parallel and spaced arrangement and a bonding material extending across the plurality of yarn strands. The bonding material encapsulates a portion of each yarn strand to bond adjacent ones of the plurality of yarn strands together.Type: ApplicationFiled: October 16, 2024Publication date: February 6, 2025Applicant: NIKE, Inc.Inventors: EunYoung Byun, Kevin R. Derr, Martin E. Evans, HoEun Kim, Eun Kyung Lee, Gwen Marks, Matthew D. Nordstrom, Todd A. Waatti, Chun-Hao Hsu, HyunWoo Jeon, Hyo Young Kim, TaeYoon Kim, I-Han Lan, Yi-Chia Liang
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Patent number: D1064350Type: GrantFiled: April 26, 2023Date of Patent: February 25, 2025Assignee: LUCIDITY ENTERPRISE CO., LTD.Inventors: Tong-Ruei Guo, Chin-Chia Hsu