Patents by Inventor Chia-Hua Lin
Chia-Hua Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11952662Abstract: Disclosed is a powder atomic layer deposition equipment with a quick release function, comprising a vacuum chamber, a shaft sealing device, and a driving unit connected to the shaft sealing device. The vacuum chamber is connected to the shaft sealing device, and an enclosed space is formed between the vacuum chamber and the shaft sealing device. At least one air extraction line is located in the shaft sealing device and fluidly connected to the enclosed space, the air extraction line being used in pumping gas out from the enclosed space to fix the vacuum chamber to the shaft sealing device so that the drive unit rotates the vacuum chamber via the shaft sealing device to facilitate the formation of a uniform thin film on powder surface. When the pumping stops, the vacuum chamber can be quickly released from the shaft sealing device to improve the process efficiency and convenience of use.Type: GrantFiled: October 18, 2021Date of Patent: April 9, 2024Assignee: SKY TECH INC.Inventors: Jing-Cheng Lin, Jung-Hua Chang, Chia-Cheng Ku
-
Patent number: 11950424Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.Type: GrantFiled: June 7, 2021Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Ting Tsai, Ching-Tzer Weng, Tsung-Hua Yang, Kao-Chao Lin, Chi-Wei Ho, Chia-Ta Hsieh
-
Publication number: 20240105504Abstract: A semiconductor device includes an insulating base layer, a semiconductor layer, an insulating layer, an isolation trench and a gettering site. The semiconductor layer and the insulating layer are disposed on the insulating base layer in sequence, and the isolation trench is disposed in the semiconductor layer and passes through the insulating layer. The isolation trench includes a first cross-section, a second cross-section and a third cross-section from top to bottom. The first cross-section is higher than the bottom surface of the insulating layer, and the second cross-section and the third cross-section are lower than the bottom surface of the insulating layer. The gettering site is disposed in the semiconductor layer and in contact with the isolation trench, and the vertex of the gettering site is lower than the second cross-section.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Applicant: Vanguard International Semiconductor CorporationInventors: Chrong-Jung Lin, Chia-Shen Liu, Wen-Hua Wen
-
Publication number: 20240105642Abstract: A method of manufacturing a package structure at least includes the following steps. An encapsulant laterally is formed to encapsulate the die and the plurality of through vias. A plurality of first connectors are formed to electrically connect to first surfaces of the plurality of through vias. A warpage control material is formed over the die, wherein the warpage control material is disposed to cover an entire surface of the die. A protection material is formed over the encapsulant and around the plurality of first connectors and the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.Type: ApplicationFiled: November 29, 2023Publication date: March 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Jan Pei, Ching-Hua Hsieh, Hsiu-Jen Lin, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu, Cheng-Shiuan Wong
-
Publication number: 20240107731Abstract: The present disclosure provides a matte-type electromagnetic interference shielding film including bio-based components, which includes a bio-based insulating layer, a bio-based adhesive layer, a metal layer, and a bio-based electrically conductive adhesive layer. The matte-type electromagnetic interference shielding film including the bio-based component of the present disclosure has a matte appearance and high bio-based content and has the advantages of good surface insulation, high surface hardness, good chemical resistance, high shielding performance, good adhesion strength, low transmission loss, high transmission quality, good operability, high heat resistance, and the inner electrically conductive adhesive layer with long shelf life and storage life. The present disclosure further provides a preparation method thereof.Type: ApplicationFiled: July 14, 2023Publication date: March 28, 2024Inventors: Bo-Sian DU, Wei-Chih LEE, Chia-Hua HO, Chih-Ming LIN, Chien-Hui LEE
-
Patent number: 11942464Abstract: In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.Type: GrantFiled: July 19, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Jan Pei, Hsiu-Jen Lin, Wei-Yu Chen, Philip Yu-Shuan Chung, Chia-Shen Cheng, Kuei-Wei Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
-
Publication number: 20240088062Abstract: A package structure includes a die, an encapsulant laterally encapsulating the die, a warpage control material disposed over the die, and a protection material disposed over the encapsulant and around the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.Type: ApplicationFiled: November 23, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Jan Pei, Ching-Hua Hsieh, Hsiu-Jen Lin, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu, Cheng-Shiuan Wong
-
Publication number: 20240087879Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
-
Publication number: 20240079483Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a fin base disposed on the substrate, nanostructured channel regions disposed on a first portion of the fin base, a gate structure surrounding the nanostructured channel regions, a source/drain (S/D) region disposed on a second portion of the fin base, and an isolation structure disposed between the S/D region and the second portion of the fin base. The isolation structure includes an undoped semiconductor layer disposed on the second portion of the fin base, a silicon-rich dielectric layer disposed on the undoped semiconductor layer, and an air spacer disposed on the silicon-rich dielectric layer.Type: ApplicationFiled: March 22, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Hung LIN, I-Hsieh WONG, Tzu-Hua CHIU, Cheng-Yi PENG, Chia-Pin LIN
-
Patent number: 11923409Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.Type: GrantFiled: August 5, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
-
Publication number: 20240071953Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
-
Publication number: 20240071954Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.Type: ApplicationFiled: November 9, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
-
Publication number: 20240021513Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a plurality of conductive contacts overlying a semiconductor substrate. A plurality of first conductive wires is disposed on the plurality of conductive contacts. A plurality of conductive vias overlies the first conductive wires. An etch stop structure is disposed on the first conductive wires. The plurality of conductive vias extend through the etch stop structure. The etch stop structure includes a first etch stop layer, a first insulator layer, and a second etch stop layer. The first insulator layer is disposed between the first etch stop layer and the second etch stop layer.Type: ApplicationFiled: January 4, 2023Publication date: January 18, 2024Inventors: Yung-Chang Chang, Lee-Chuan Tseng, Chia-Hua Lin, Shu-Hui Su
-
Publication number: 20230413682Abstract: A semiconductor structure includes a bottom electrode, a magnetic tunneling junction stack over the bottom electrode, a top electrode over the magnetic tunneling junction stack, a first dielectric layer under the bottom electrode, a second dielectric layer under the first dielectric layer. The first dielectric layer has a first chemical bond energy and the second dielectric layer has a second chemical bond energy less than the first chemical bond energy.Type: ApplicationFiled: June 10, 2022Publication date: December 21, 2023Inventors: Chia-Hua LIN, Yao-Wen CHANG
-
Publication number: 20230389445Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a memory cell stack over a substrate. The memory cell stack includes a top electrode. A sidewall spacer structure is formed around the memory cell stack. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. A dielectric structure is formed over the sidewall spacer structure. A first etch process is performed on the dielectric structure and the second sidewall spacer layer to define an opening above the top electrode. The second sidewall spacer layer and the dielectric structure are etched at a higher rate than the protective sidewall spacer layer during the first etch process. A top electrode via is formed within the opening.Type: ApplicationFiled: August 3, 2023Publication date: November 30, 2023Inventors: Yao-Wen Chang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsung-Hsueh Yang, Yuan-Tai Tseng, Sheng-Huang Huang, Chia-Hua Lin
-
Publication number: 20230375182Abstract: A method for controlling a heating process may include recognizing a food class of a food item, defining a target doneness score for the food item based on at least one of the food class and a desired doneness level, receiving a food humidity level, receiving a cavity humidity level, receiving a cavity temperature, determining a current doneness score of the food item according to the food humidity level, the cavity humidity level and the cavity temperature, and utilizing the current doneness score and the target doneness score to control a heating system to cook the food item.Type: ApplicationFiled: May 20, 2022Publication date: November 23, 2023Inventors: Blake W. EHRENBECK, Seth HERNDON, Chia-Hua LIN, Bruce M. WIATRAK
-
Patent number: 11818962Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a memory cell stack over a substrate. The memory cell stack includes a top electrode. A sidewall spacer structure is formed around the memory cell stack. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. A dielectric structure is formed over the sidewall spacer structure. A first etch process is performed on the dielectric structure and the second sidewall spacer layer to define an opening above the top electrode. The second sidewall spacer layer and the dielectric structure are etched at a higher rate than the protective sidewall spacer layer during the first etch process. A top electrode via is formed within the opening.Type: GrantFiled: August 19, 2021Date of Patent: November 14, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yao-Wen Chang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsung-Hsueh Yang, Yuan-Tai Tseng, Sheng-Huang Huang, Chia-Hua Lin
-
Patent number: 11721794Abstract: A method for manufacturing reflective structure is provided. The method includes the operations as follows. A metallization structure is received. A plurality of conductive pads are formed over the metallization structure. A plurality of dielectric stacks are formed over the conductive pads, respectively, wherein the thicknesses of the dielectric stacks are different. The dielectric stacks are isolated by forming a plurality of trenches over a plurality of intervals between each two adjacent dielectric stacks.Type: GrantFiled: February 18, 2022Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chia-Hua Lin, Yao-Wen Chang, Chii-Ming Wu, Cheng-Yuan Tsai, Eugene I-Chun Chen, Tzu-Chung Tsai
-
Patent number: 11682692Abstract: In some embodiments, the present disclosure relates to a display device that includes a reflector electrode coupled to an interconnect structure. An isolation structure is disposed over the reflector electrode, and a transparent electrode is disposed over the isolation structure. Further, an optical emitter structure is disposed over the transparent electrode. A via structure extends from a top surface of the isolation structure to the reflector electrode and comprises an outer portion that directly overlies the top surface of the isolation structure. A hard mask layer is arranged directly between the top surface of the isolation structure and the outer portion of the via structure.Type: GrantFiled: May 11, 2020Date of Patent: June 20, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hua Lin, Hsun-Chung Kuang, Yu-Hsing Chang, Yao-Wen Chang
-
Patent number: D990430Type: GrantFiled: October 27, 2021Date of Patent: June 27, 2023Inventor: Chia-Hua Lin