Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.

Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes first and second gates, a dielectric hump, a first spacer, a charge storage layer, a gate dielectric layer, a high-k layer and doped regions. The first and the second gates are disposed on a substrate. The dielectric hump is disposed on the substrate between the first gate and the second gate. The first spacer is disposed on a sidewall of the dielectric hump. The charge storage layer is disposed between the first gate and the substrate. The gate dielectric layer is disposed between the second gate and the substrate. The high-k layer is disposed between the first gate and the charge storage layer and between the second gate and the gate dielectric layer. The doped regions are disposed in the substrate at two sides of the first gate and at two sides of the second gate.

Abstract: A power connection assembly includes a housing, a plug, and a first and a second conductive member. The housing has a first opening. The plug is disposed in the housing, and includes a first rotating base, and a first and a second electrode terminal. The first rotating base is movably fitted into the first opening. The first and the second electrode terminal penetrate through the first rotating base to form a first and a second contact portion. The first conductive member includes a first clamping portion that includes two second elastic sheets. Each second elastic sheet has a first and a second elastic segment. The first elastic segment is L-shaped, and the second elastic segment is cylindrical. The second elastic segments of the two second elastic sheets are configured to clamp the first electrode terminal, so that the first electrode terminal electrically contacts the first conductive member.

Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes a substrate having first and second regions, first and second isolation structures in the substrate, a charge storage layer on the substrate, first and second gates and doped regions. The first isolation structures define first active areas in the first region. A top surface of the first isolation structure is higher than that of the substrate. The second isolation structures define second active areas in the second region. A top surface of the second isolation structure is lower than that of the substrate. The first gate is on the charge storage layer in the first active area. The second gate is on the charge storage layer in the second active area. The doped regions are in the substrate at two sides of the first gate and at two sides of the second gate.

Abstract: A method for fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer; depositing a second dielectric layer over the first dielectric layer; etching a trench opening in the second dielectric layer, wherein the trench opening exposes a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer, the first sidewall of the second dielectric layer extends substantially along a first direction, and the second sidewall of the second dielectric layer extends substantially along a second direction different from the first direction in a top view; forming a via etch stop layer on the first sidewall of the second dielectric layer, wherein the second sidewall of the second dielectric layer is free from coverage by the via etch stop layer; forming a conductive line in the trench opening; and forming a conductive via over the conductive line.

Abstract: An electronic device includes a substrate, a sidewall, a plurality of light emitting elements and an optical element. The sidewall is connected to the substrate. The plurality of light emitting elements are disposed on the substrate. The optical element covers at least two of the plurality of light emitting elements, wherein, in a cross-sectional view of the electronic device, a portion of the optical element is disposed between two adjacent ones of the plurality of light emitting elements, and a height of the sidewall is greater than a thickness of the optical element.

Abstract: An inductor assembly includes a first magnetic core, a second magnetic core, a winding and a bonding material layer. The second magnetic core includes a channel. The winding is disposed within the channel. The bonding material layer is disposed between the first magnetic core and the second magnetic core and includes a first bonding material and a second bonding material. A magnetic permeability of the first bonding material is greater than a magnetic permeability of the second bonding material. The first bonding material and the second bonding material are disposed on the second magnetic core. A surface of the first bonding material faced to the first magnetic core and a surface of the second bonding material faced to the first magnetic core are coplanar with each other.

Abstract: An immersion cooling system includes a cooling tank, a housing and a valve. The coolant tank is configured to accommodate a liquid coolant and an electronic device immersed in the liquid coolant. The housing covers a side of the cooling tank and thereby forms an enclosure. The valve has two ports, one of which communicates with the enclosure and the other communicates with a part of the cooling tank above the liquid coolant. The valve is configured to open in response to a gas pressure inside the cooling tank exceeding an upper limit.

Abstract: Systems and methods are provided for an electronic device that comprises a core logic circuit coupled to a supply voltage rail and an operating voltage rail. During a standard operation, the supply voltage rail has a supply voltage, the operating voltage rail has an operating voltage, and a post driver voltage rail has an overdrive voltage that is greater than the operating voltage. The electronic device further comprises a first power clamp circuit coupled to the supply voltage rail and the post driver voltage rail, a low-side logic-high voltage rail coupled to the first end of the core logic circuit, and a first power-to-power clamp circuit coupled to the low-side logic-high voltage rail and the post driver voltage rail. The first power-to-power clamp circuit is configured to receive electrostatic discharge (ESD) current between the post driver voltage rail and the low-side logic-high voltage rail.

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

Abstract: Provided herein are methods of assaying a methylated DNA-binding protein comprising contacting methylated DNA-binding proteins with labeled oligonucleotides, obtaining sample partitions for oligonucleotides with different methylation states, and quantifying the labeled oligonucleotides in the partitions.

Abstract: A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.

Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.

Abstract: Disclosed herein are related to a device for electrostatic discharge (ESD) protection. In one aspect, a device includes an ESD detector to detect an ESD at a pad. In one aspect, the device includes P-type transistors and N-type transistors connected in series with each other. In one aspect, the drive circuit is configured to provide an output signal to the pad. In one aspect, the device includes a first protection circuit operating in a power domain. In one aspect, in response to the ESD detected by the ESD detector, the first protection circuit is configured to disable the P-type transistors. In one aspect, the device includes a second protection circuit operating in another power domain. In one aspect, in response to the ESD detected by the ESD detector, the second protection circuit is configured to disable the N-type transistors.

Abstract: An IC driver includes a cascode arrangement of first-type transistors coupled in series with a cascode arrangement of second-type transistors different from the first-type transistors. Each cascode arrangement includes an active area extending in a first direction, gate structures extending perpendicular to the first direction and overlying the active area at locations corresponding to the transistors of the cascode arrangement, first through fourth metal segments extending in the first direction in a first metal layer of the IC, first and second vias electrically coupling respective first and second gate structures to the first and second metal segments, a third via electrically coupling a source terminal of the cascode arrangement to the third metal segment, and a fourth via electrically coupling a drain terminal of the cascode arrangement to the fourth metal segment. The third and fourth metal segments are aligned along the first direction.

Abstract: An integrated circuit including: substrates stacked one over another, the substrates including first to fourth substrates having a P-type doping; the first substrate including a first set of electrical components on one or more of the substrates and forming a first circuit; a first ground reference rail connected to the first circuit; a first power supply rail connected between the first power supply rail and the first ground reference rail; a first electrostatic discharge (ESD) conduction element, connected between the first ground reference rail and a first part of a common ground reference rail, including a first diode in the second substrate and a second diode in the first substrate; the first diode and the second diode being connected in parallel, having different dopant types and having opposite polarities; and a second part of the common ground reference rail being connected to the third substrate and the fourth substrate.

Abstract: Disclosed herein are related to a device for electrostatic discharge (ESD) protection. In one aspect, a device includes an ESD detector to detect an ESD at a pad. In one aspect, the device includes P-type transistors and N-type transistors connected in series with each other. In one aspect, the drive circuit is configured to provide an output signal to the pad. In one aspect, the device includes a first protection circuit operating in a power domain. In one aspect, in response to the ESD detected by the ESD detector, the first protection circuit is configured to disable the P-type transistors. In one aspect, the device includes a second protection circuit operating in another power domain. In one aspect, in response to the ESD detected by the ESD detector, the second protection circuit is configured to disable the N-type transistors.

Abstract: A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.

Abstract: An integrated circuit includes an upper threshold circuit configured to set a logic level of a first enabling signal, a lower threshold circuit configured to set a logic level of a second enabling signal, and a control circuit configured to change an output voltage signal in response to a condition that the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively. In the control circuit, a first switch is electrically connected to a second switch at a buffer output node. The control circuit includes a regenerative circuit configured to maintain the output voltage signal at the buffer output node while each of the first switch and the second switch is at a disconnected state.

Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.