Abstract: A display panel including a circuit board, a plurality of bonding pads, a plurality of light emitting devices, and a plurality of solder patterns is provided. The bonding pads are disposed on the circuit board, and each includes a first metal layer and a second metal layer. The second metal layer is located between the first metal layer and the circuit board. The first metal layer includes an opening overlapping the second metal layer. A material of the first metal layer is different from a material of the second metal layer. The light emitting devices are electrically bonded to the bonding pads. Each of the solder patterns electrically connects one of the light emitting devices and one of the bonding pads. The solder patterns each contact the second metal layer through the opening of the first metal layer of one of the bonding pads to form a eutectic bonding.

Abstract: A method includes etching a gate stack in a wafer to form a trench, depositing a silicon nitride liner extending into the trench, and depositing a silicon oxide layer. The process of depositing the silicon oxide layer includes performing a treatment process on the wafer using a process gas including nitrogen and hydrogen, and performing a soaking process on the wafer using a silicon precursor.

Abstract: The present disclosure provides a matte-type electromagnetic interference shielding film including bio-based components, which includes a bio-based insulating layer, a bio-based adhesive layer, a metal layer, and a bio-based electrically conductive adhesive layer. The matte-type electromagnetic interference shielding film including the bio-based component of the present disclosure has a matte appearance and high bio-based content and has the advantages of good surface insulation, high surface hardness, good chemical resistance, high shielding performance, good adhesion strength, low transmission loss, high transmission quality, good operability, high heat resistance, and the inner electrically conductive adhesive layer with long shelf life and storage life. The present disclosure further provides a preparation method thereof.

Abstract: In an embodiment, a package includes a first device and a second device attached to a first redistribution structure, wherein the second device includes a second redistribution structure, a first die disposed over the second redistribution structure, a first encapsulant extending along sidewalls of the first die, a first via extending through the first encapsulant, a third redistribution structure disposed over the first encapsulant and including a first metallization pattern connecting to the first via, a second die disposed over the third redistribution structure, and a second encapsulant extending along sidewalls of the second die, the first die and the second die being free of through substrate vias. The package also includes a third encapsulant disposed over the first redistribution structure and surrounding sidewalls of the first device and the second device, wherein top surfaces of the second encapsulant and the third encapsulant are level with each other.

Abstract: A high-throughput automated preprocessing method and a system are applied to a nucleic acid preprocessing apparatus including a control system, a sample transfer area, a nucleic acid extraction area, and a reagent setup area. The control system includes a user interface and guides a user to set up on the user interface. In the sample transfer area, the method includes steps of: a user selecting a sampling tube type, a test protocol and an extraction protocol on the user interface, and the control system performing a sample transfer task. In the nucleic acid extraction area, the method includes steps of: the control system performing a nucleic acid extraction task based on the selected extraction protocol. In the reagent setup area, the method includes steps of: the control system performing a reagent deployment task based on the selected test protocol, and the control system performing a nucleic acid transfer task.

Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

Abstract: The present disclosure provides an electronic device including a substrate, a first circuit layer, and a plurality of diodes. The substrate has a plurality of first through holes. The first circuit layer is disposed on the substrate and has a plurality of light through holes. The diodes disposed on the first circuit layer. One of the light through holes is located between two adjacent ones of the diodes, and the light through holes overlap a portion of the plurality of first through holes and do not overlap another portion of the plurality of first through holes in a normal direction of the substrate.

Abstract: An electronic device is disclosed and includes a substrate, a circuit layer, and a plurality of diodes. The substrate has a plurality of structures. The circuit layer is disposed on the substrate. The diodes are disposed on the circuit layer, wherein a first spacing is defined as a distance between a center point of a first one of the structures and a center point of a second one of the structures, a second spacing is defined as a distance between a center point of a third one of the structures and a center point of a fourth one of the structures, and an absolute value of a difference between the first spacing and the second spacing is less than 0.5 times radius of curvature of the electronic device when the electronic device is bent.

Abstract: A semiconductor die, a semiconductor package and manufacturing methods thereof are provided. The semiconductor die includes: a front-end-of-line (FEOL) structure, built on a semiconductor substrate; a back-end-of-line (BEOL) structure, formed on the FEOL structure, and including a stack of metallization layers; and bonding metals, disposed on the BEOL structure. The bonding metals include: a conductive pad, disposed over the BEOL structure, and electrically connected to the metallization layers in the BEOL structure; a conductive capping layer, lining along a top surface of the conductive pad; and an engaging feature, landing on the conductive capping layer and separated from the conductive pad by the conductive capping layer. The semiconductor die is bonded to another semiconductor die or a package component by the engaging feature.

Abstract: An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls.

Abstract: An electronic device is disclosed and includes a substrate, a circuit layer, and a plurality of diodes. The substrate has a plurality of structures. The circuit layer is disposed on the substrate. The diodes are disposed on the circuit layer, wherein a first spacing is defined as a distance between a center point of a first one of the structures and a center point of a second one of the structures, a second spacing is defined as a distance between a center point of a third one of the structures and a center point of a fourth one of the structures, and an absolute value of a difference between the first spacing and the second spacing is less than 0.5 times radius of curvature of the electronic device when the electronic device is bent.

Abstract: An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls.

Abstract: An electronic device is disclosed and includes a base substrate, a circuit layer, and a plurality of light-emitting elements. The base substrate has a plurality of through holes, the circuit layer is disposed on the base substrate, and the light-emitting elements are disposed on the first circuit layer. An absolute value of a difference between two adjacent spacings of the plurality of through holes of the base substrate is less than 0.5 times radius of curvature of the electronic device when the electronic device is bent.

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

Abstract: A method for testing LEDs includes: Step 1: providing a wafer including a plurality of LEDs and selecting N LEDs from the plurality of LEDs to form an LED group; Step 2: selecting n LEDs from the LED group, where 1<n<N, and testing the n LEDs at a time to obtain a subgroup optical parameter of the LED group; Step 3: performing the Step 2 on the N LEDs repeatedly and alternately for another n LEDs in the LED group to obtain a plurality of the subgroup optical parameters; and Step 4: obtaining an optical parameter of each of the LEDs in the LED group from the plurality of the subgroup optical parameters.

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure, a source/drain structure, a barrier layer, and a glue layer. The gate structure is over a fin structure. The source/drain structure is in the fin structure and adjacent to the gate structure. The barrier layer is over the source/drain structure. The glue layer is adjacent to the barrier layer. The glue layer has an extending portion in direct contact with the gate structure.

Abstract: An electronic device is disclosed and includes a base substrate, a circuit layer, and a plurality of light-emitting elements. The base substrate has a plurality of through holes, the circuit layer is disposed on the base substrate, and the light-emitting elements are disposed on the first circuit layer. An absolute value of a difference between two adjacent spacings of the plurality of through holes of the base substrate is less than 0.5 times radius of curvature of the electronic device when the electronic device is bent.

Abstract: Provided herein are methods of determining that a subject has or is at risk of having a disease (e.g., cancer) using nucleic acid molecules derived from a cell-free biological sample of the subject.