Patents by Inventor Chia-Hui Lin
Chia-Hui Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250044708Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.Type: ApplicationFiled: October 18, 2024Publication date: February 6, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Gun LIU, Huicheng CHANG, Chia-Cheng CHEN, Jyu-Horng SHIEH, Liang-Yin CHEN, Shu-Huei SUEN, Wei-Liang LIN, Ya Hui CHANG, Yi-Nien SU, Yung-Sung YEN, Chia-Fong CHANG, Ya-Wen YEH, Yu-Tien SHEN
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Publication number: 20250043337Abstract: Provided herein are methods of assaying a methylated DNA-binding protein comprising contacting methylated DNA-binding proteins with labeled oligonucleotides, obtaining sample partitions for oligonucleotides with different methylation states, and quantifying the labeled oligonucleotides in the partitions.Type: ApplicationFiled: May 10, 2024Publication date: February 6, 2025Inventors: Saiyou OHSHIMA, Kenneth Edmund STAPLETON, Dustin Howard HITE, Xiao-Bo CHEN, Chia-Hui LIN, Dania ANNUAR, Jessica Michelle PIERACCI
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Publication number: 20250031920Abstract: A window cleaning machine provided according to an embodiment of the disclosure comprises a resilient member disposed between a body and a first cleaning device to prevent external air from passing between the body and the first cleaning device and entering a primary suction space of the body.Type: ApplicationFiled: May 20, 2024Publication date: January 30, 2025Inventors: CHI-MOU CHAO, HSIN-HUI WU, CHIA-CHIN LIN
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Publication number: 20250031922Abstract: A window cleaning machine includes a body, walking module, air extracting module, first cleaning device and driving device. The body defines a primary suction space. The walking module is disposed near the body. The air extracting module is disposed on the body and is in communication with the primary suction space, allowing the body to cling to the pane surface by suction. The first cleaning device is in contact with the pane surface while performing a cleaning operation. The driving device is connected to the first cleaning device to cause the first cleaning device to undergo a reciprocating motion so as to wipe the pane surface back and forth. The body further comprises a bottom board and a carrying board. The bottom board comprises a bottom board wall portion enclosing a first bottom board through hole. The carrying board is disposed between the first cleaning device and the bottom board.Type: ApplicationFiled: May 20, 2024Publication date: January 30, 2025Inventors: CHI-MOU CHAO, HSIN-HUI WU, CHIA-CHIN LIN
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Publication number: 20250031921Abstract: Provided is a window cleaning machine including a body, air extracting module, first cleaning device, second cleaning device, walking module disposed near the body, and driving device connected to the first and second cleaning devices to cause a reciprocating motion thereof. The body defines a primary suction space. The air extracting module is disposed on the body and is in communication with the primary suction space. The first and second cleaning devices are each in contact with a pane surface while performing a cleaning operation. The first cleaning device defines a first subsidiary space in communication with the primary suction space. The second cleaning device defines a second subsidiary space in communication with the primary suction space. The walking module is disposed outside the first and second subsidiary spaces. The window cleaning machine undergoes the reciprocating motion across a non-horizontal pane surface while clinging firmly thereto by suction.Type: ApplicationFiled: May 20, 2024Publication date: January 30, 2025Inventors: CHI-MOU CHAO, HSIN-HUI WU, CHIA-CHIN LIN
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Patent number: 12205501Abstract: The present disclosure provides an electronic device including a substrate, a plurality of bumps, a plurality of diodes, and a shielding layer. The substrate has a plurality of first through holes. The bumps are disposed on the substrate. The diodes are disposed on the substrate. The shielding layer is disposed on the substrate. One of the bumps is located between two adjacent ones of the diodes in a cross-sectional view, and the shielding layer overlaps at least a portion of the bumps and at least a portion of the first through holes.Type: GrantFiled: May 22, 2024Date of Patent: January 21, 2025Assignee: InnoLux CorporationInventors: Chin-Lung Ting, Chung-Kuang Wei, Li-Wei Mao, Chi-Liang Chang, Chia-Hui Lin
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Publication number: 20250024671Abstract: A memory device is provided which includes a first memory cell including a first transistor and a second transistor coupled to the first transistor in parallel. Gates of the first transistor and the second transistor are coupled to each other, and the gates of the first transistor and the second transistor pass different layers and overlap with each other. Types of the first transistor and the second transistor are the same.Type: ApplicationFiled: July 11, 2023Publication date: January 16, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien Hui Huang, Kao-Cheng LIN, Wei Min CHAN, Shang Lin WU, Chia-Chi HUNG, Wei-Cheng WU, Chia-Che CHUNG, Pei-Yuan LI, Chien-Chen LIN, Yung-Ning TU, Yen Lin CHUNG
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Patent number: 12188974Abstract: A method for testing LEDs includes: Step 1: providing a wafer including a plurality of LEDs and selecting N LEDs from the plurality of LEDs to form an LED group; Step 2: selecting n LEDs from the LED group, where 1<n<N, and testing the n LEDs at a time to obtain a subgroup optical parameter of the LED group; Step 3: performing the Step 2 on the N LEDs repeatedly and alternately for another n LEDs in the LED group to obtain a plurality of the subgroup optical parameters; and Step 4: obtaining an optical parameter of each of the LEDs in the LED group from the plurality of the subgroup optical parameters.Type: GrantFiled: April 11, 2022Date of Patent: January 7, 2025Assignee: EPISTAR CORPORATIONInventors: Sheng Jie Hsu, Chia Hui Lin, Po Chun Liu
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Publication number: 20240363707Abstract: A semiconductor device is provided. The semiconductor device includes a source/drain structure, a contact structure, a glue layer, a barrier layer, and a silicide layer. The contact structure is over the source/drain structure. The glue layer surrounds the contact structure. The barrier layer is formed on at least a portion of a sidewall surface of the contact structure. The silicide layer is between the source/drain structure and the contact structure, and the silicide layer is in direct contact with the glue layer. The bottom surface of the glue layer is lower than the top surface of the source/drain structure and the bottom surface of the barrier layer.Type: ApplicationFiled: July 10, 2024Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wen HUANG, Chung-Ting KO, Hong-Hsien KE, Chia-Hui LIN, Tai-Chun HUANG
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Publication number: 20240312375Abstract: The present disclosure provides an electronic device including a substrate, a plurality of bumps, a plurality of diodes, and a shielding layer. The substrate has a plurality of first through holes. The bumps are disposed on the substrate. The diodes are disposed on the substrate. The shielding layer is disposed on the substrate. One of the bumps is located between two adjacent ones of the diodes in a cross-sectional view, and the shielding layer overlaps at least a portion of the bumps and at least a portion of the first through holes.Type: ApplicationFiled: May 22, 2024Publication date: September 19, 2024Applicant: InnoLux CorporationInventors: Chin-Lung Ting, Chung-Kuang Wei, Li-Wei Mao, Chi-Liang Chang, Chia-Hui Lin
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Patent number: 12087834Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure, a source/drain structure, a barrier layer, and a glue layer. The gate structure is over a fin structure. The source/drain structure is in the fin structure and adjacent to the gate structure. The barrier layer is over the source/drain structure. The glue layer is adjacent to the barrier layer. The glue layer has an extending portion in direct contact with the gate structure.Type: GrantFiled: March 4, 2022Date of Patent: September 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Wen Huang, Chung-Ting Ko, Hong-Hsien Ke, Chia-Hui Lin, Tai-Chun Huang
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Publication number: 20240282638Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.Type: ApplicationFiled: April 16, 2024Publication date: August 22, 2024Inventors: Shih-Wen Huang, Jaming Chang, Kai Hung Cheng, Chia-Hui Lin, Jei Ming Chen
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Patent number: 12020602Abstract: The present disclosure provides an electronic device including a substrate, a first circuit layer, and a plurality of diodes. The substrate has a plurality of first through holes. The first circuit layer is disposed on the substrate and has a plurality of light through holes. The diodes disposed on the first circuit layer. One of the light through holes is located between two adjacent ones of the diodes, and the light through holes overlap a portion of the plurality of first through holes and do not overlap another portion of the plurality of first through holes in a normal direction of the substrate.Type: GrantFiled: September 26, 2023Date of Patent: June 25, 2024Assignee: InnoLux CorporationInventors: Chin-Lung Ting, Chung-Kuang Wei, Li-Wei Mao, Chi-Liang Chang, Chia-Hui Lin
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Patent number: 11990375Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.Type: GrantFiled: June 29, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Wen Huang, Jaming Chang, Kai Hung Cheng, Chia-Hui Lin, Jei Ming Chen
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Publication number: 20240120236Abstract: A method includes etching a gate stack in a wafer to form a trench, depositing a silicon nitride liner extending into the trench, and depositing a silicon oxide layer. The process of depositing the silicon oxide layer includes performing a treatment process on the wafer using a process gas including nitrogen and hydrogen, and performing a soaking process on the wafer using a silicon precursor.Type: ApplicationFiled: April 25, 2023Publication date: April 11, 2024Inventors: Tai-Jung Kuo, Po-Cheng Shih, Wan Chen Hsieh, Zhen-Cheng Wu, Chia-Hui Lin, Tze-Liang Lee
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Publication number: 20240096722Abstract: In an embodiment, a package includes a first device and a second device attached to a first redistribution structure, wherein the second device includes a second redistribution structure, a first die disposed over the second redistribution structure, a first encapsulant extending along sidewalls of the first die, a first via extending through the first encapsulant, a third redistribution structure disposed over the first encapsulant and including a first metallization pattern connecting to the first via, a second die disposed over the third redistribution structure, and a second encapsulant extending along sidewalls of the second die, the first die and the second die being free of through substrate vias. The package also includes a third encapsulant disposed over the first redistribution structure and surrounding sidewalls of the first device and the second device, wherein top surfaces of the second encapsulant and the third encapsulant are level with each other.Type: ApplicationFiled: January 10, 2023Publication date: March 21, 2024Inventors: Kuo-Chung Yee, Chia-Hui Lin, Shih-Peng Tai
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Publication number: 20240021113Abstract: The present disclosure provides an electronic device including a substrate, a first circuit layer, and a plurality of diodes. The substrate has a plurality of first through holes. The first circuit layer is disposed on the substrate and has a plurality of light through holes. The diodes disposed on the first circuit layer. One of the light through holes is located between two adjacent ones of the diodes, and the light through holes overlap a portion of the plurality of first through holes and do not overlap another portion of the plurality of first through holes in a normal direction of the substrate.Type: ApplicationFiled: September 26, 2023Publication date: January 18, 2024Applicant: InnoLux CorporationInventors: Chin-Lung Ting, Chung-Kuang Wei, Li-Wei Mao, Chi-Liang Chang, Chia-Hui Lin
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Patent number: 11810485Abstract: An electronic device is disclosed and includes a substrate, a circuit layer, and a plurality of diodes. The substrate has a plurality of structures. The circuit layer is disposed on the substrate. The diodes are disposed on the circuit layer, wherein a first spacing is defined as a distance between a center point of a first one of the structures and a center point of a second one of the structures, a second spacing is defined as a distance between a center point of a third one of the structures and a center point of a fourth one of the structures, and an absolute value of a difference between the first spacing and the second spacing is less than 0.5 times radius of curvature of the electronic device when the electronic device is bent.Type: GrantFiled: December 6, 2022Date of Patent: November 7, 2023Assignee: InnoLux CorporationInventors: Chin-Lung Ting, Chung-Kuang Wei, Li-Wei Mao, Chi-Liang Chang, Chia-Hui Lin
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Publication number: 20230352418Abstract: A semiconductor die, a semiconductor package and manufacturing methods thereof are provided. The semiconductor die includes: a front-end-of-line (FEOL) structure, built on a semiconductor substrate; a back-end-of-line (BEOL) structure, formed on the FEOL structure, and including a stack of metallization layers; and bonding metals, disposed on the BEOL structure. The bonding metals include: a conductive pad, disposed over the BEOL structure, and electrically connected to the metallization layers in the BEOL structure; a conductive capping layer, lining along a top surface of the conductive pad; and an engaging feature, landing on the conductive capping layer and separated from the conductive pad by the conductive capping layer. The semiconductor die is bonded to another semiconductor die or a package component by the engaging feature.Type: ApplicationFiled: April 27, 2022Publication date: November 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Lin, Po-Hsun Chang, Yu-Kuang Liao, Chia-Hui Lin, Shih-Peng Tai, Kuo-Chung Yee
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Publication number: 20230197524Abstract: An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls.Type: ApplicationFiled: February 13, 2023Publication date: June 22, 2023Inventors: Chun-Yi Lee, Hong-Hsien Ke, Chung-Ting Ko, Chia-Hui Lin, Jr-Hung Li