Patents by Inventor Chia-Hui Lin

Chia-Hui Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210233813
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.
    Type: Application
    Filed: April 12, 2021
    Publication date: July 29, 2021
    Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih Pei Chou, Chia-Chieh Lin
  • Patent number: 11073726
    Abstract: A display device including a backlight module is provided. The backlight module includes: a substrate, a backlight cavity, a plurality of light emitting elements, and an optical adjustment layer. The backlight cavity is located on the substrate. The plurality of light emitting elements is disposed in the backlight cavity. The optical adjustment layer covers the plurality of light emitting elements and fills the remaining space of the backlight cavity. The optical adjustment layer has a refractive index n greater than the refractive index n0 of the air.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: July 27, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Chin-Lung Ting, Ming-Hui Chu, Fang-Ho Lin, Chia-Lun Chen, Yen-Liang Chen
  • Patent number: 11049945
    Abstract: Semiconductor device structures and methods for forming the same are provided. A semiconductor device structure includes a gate structure over a semiconductor substrate. The gate structure includes a gate electrode layer and a gate dielectric layer covering a bottom surface and sidewalls of the gate electrode layer. The semiconductor device structure also includes spacer elements in contact with sidewalls of the gate structure and protruding from a top surface of the gate electrode layer. The semiconductor device structure also includes a first protection layer over the gate electrode layer and between the spacer elements. The semiconductor device structure also includes a dielectric layer over the first protection layer and between the spacer elements. A portion of the dielectric layer is between sidewalls of the spacer elements and sidewalls of the first protection layer.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wen Huang, Yun-Wen Chu, Hong-Hsien Ke, Chia-Hui Lin, Shin-Yeu Tsai, Shih-Chieh Chang
  • Publication number: 20210150947
    Abstract: An electronic device is disclosed and includes a base substrate, a first circuit layer and a plurality of light-emitting elements. The base substrate has a first surface and a second surface opposite to each other. The first circuit layer includes a first portion and a second portion. The first portion is disposed on the first surface of the base substrate, and the second portion is disposed on the second surface of the base substrate. The light-emitting elements are disposed on the first portion of the first circuit layer. At least one of the second surface of the base substrate and the first portion of the first circuit layer includes at least one microstructure.
    Type: Application
    Filed: January 28, 2021
    Publication date: May 20, 2021
    Inventors: Chin-Lung Ting, Chung-Kuang Wei, Li-Wei Mao, Chi-Liang Chang, Chia-Hui Lin
  • Patent number: 10957226
    Abstract: An electronic device and a tiling electronic apparatus are disclosed and include a base substrate, a first circuit layer and a plurality of light-emitting elements. The base substrate has a first surface and a second surface opposite to each other. The first circuit layer includes a first portion and a second portion. The first portion is disposed on the first surface of the base substrate, and the second portion is disposed on the second surface of the base substrate. The light-emitting elements are disposed on the first portion of the first circuit layer. At least one of the second surface of the base substrate and the first portion of the first circuit layer includes at least one microstructure.
    Type: Grant
    Filed: March 24, 2019
    Date of Patent: March 23, 2021
    Assignee: InnoLux Corporation
    Inventors: Chin-Lung Ting, Chung-Kuang Wei, Li-Wei Mao, Chi-Liang Chang, Chia-Hui Lin
  • Publication number: 20200411386
    Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Inventors: Shih-Wen Huang, Jaming Chang, Kai Hung Cheng, Chia-Hui Lin, Jei Ming Chen
  • Publication number: 20200373154
    Abstract: A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 26, 2020
    Inventors: Dong-Sheng Li, Chia-Hui Lin, Kai Hung Cheng, Yao-Hsu Sun, Wen-Cheng Wu, Bo-Cyuan Lu, Sung-En Lin, Tai-Chun Huang
  • Patent number: 10795857
    Abstract: A method includes the steps of: monitoring status information of a blockchain system; determining whether the status information meets a blockchain branch condition; when the status information matches the blockchain branch condition, writing a branch instruction to a selected block of the blockchain, wherein the branch instruction is configured to enable the blockchain to form a plurality of branches, and divide a plurality of blockchain devices in the blockchain system into a plurality of groups to verify the branches in parallel; and obtaining a maximum transmission delay time in the group, and deciding a new one to generate blocks of the first branch according to the maximum transmission delay time.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: October 6, 2020
    Assignee: Industrial Technology Research Institute
    Inventor: Chia-Hui Lin
  • Patent number: 10777466
    Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wen Huang, Chia-Hui Lin, Jaming Chang, Jei Ming Chen, Kai Hung Cheng
  • Publication number: 20200287109
    Abstract: An electronic device includes a substrate, a light-emitting element, and a spacing structure. The light-emitting element is disposed on the substrate. The spacing structure is disposed adjacent to the light-emitting element, and the spacing structure includes a first wall, a second wall, and a boundary portion. The first wall includes a first protrusion portion and extends in a first direction. The second wall includes a second protrusion portion and extends in a second direction, and the first direction is different from the second direction. The boundary portion is connected to the first protrusion portion and the second protrusion portion, and the height of the boundary portion is lower than the height of the first protrusion portion.
    Type: Application
    Filed: February 18, 2020
    Publication date: September 10, 2020
    Inventors: Chi-Liang CHANG, Fang-Ho LIN, Ya-Fen CHENG, Chia-Hui LIN, I-Chang LIANG, Hsin-Cheng HUNG
  • Patent number: 10752834
    Abstract: Disclosed herein are composite fluorescent gold nanoclusters with high quantum yield, as well as methods for manufacturing the same. According to some embodiments, the composite fluorescent gold nanocluster includes a gold nanocluster and a capping layer that encapsulates at least a portion of the outer surface of the gold nanocluster. The capping layer includes a matrix made of a benzene-based compound, and multiple phosphine-based compounds distributed across the matrix.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: August 25, 2020
    Assignee: CHUNG YUAN CHRISTIAN UNIVERSITY
    Inventors: Cheng-An Lin, Cheng-Yi Huang, Chia-Hui Lin, Tzu-Yin Hou
  • Patent number: 10734227
    Abstract: A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dong-Sheng Li, Chia-Hui Lin, Kai Hung Cheng, Yao-Hsu Sun, Wen-Cheng Wu, Bo-Cyuan Lu, Sung-En Lin, Tai-Chun Huang
  • Publication number: 20200235214
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a gate structure over a fin structure, forming a source/drain structure in the fin structure and adjacent to the gate structure, forming a dielectric layer over the gate structure and the source/drain structure, and forming an opening in the dielectric layer to expose the source/drain structure. The method further includes depositing a barrier layer lining a sidewall surface of the opening and a top surface of the source/drain structure. The method further includes etching a portion of the barrier layer to expose the source/drain structure. The method further includes depositing a glue layer covering the sidewall surface of the opening and the source/drain structure in the opening. The method further includes forming a contact structure filling the opening in the dielectric layer. The contact structure is surrounded by the glue layer.
    Type: Application
    Filed: April 2, 2020
    Publication date: July 23, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wen HUANG, Chung-Ting KO, Hong-Hsien KE, Chia-Hui LIN, Tai-Chun HUANG
  • Patent number: 10720430
    Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wen Huang, Chia-Hui Lin, Shin-Yeu Tsai, Kai Hung Cheng
  • Publication number: 20200176259
    Abstract: A method includes etching a gate structure to form a trench extending into the gate structure, wherein sidewalls of the trench comprise a metal oxide material, applying a sidewall treatment process to the sidewalls of the trench, wherein the metal oxide material has been removed as a result of applying the sidewall treatment process and filling the trench with a first dielectric material to form a dielectric region, wherein the dielectric region is in contact with the sidewall of the gate structure.
    Type: Application
    Filed: November 12, 2019
    Publication date: June 4, 2020
    Inventors: Chun-Yi Lee, Ting-Gang Chen, Chieh-Ping Wang, Hong-Hsien Ke, Chia-Hui Lin, Tai-Chun Huang
  • Publication number: 20200144258
    Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.
    Type: Application
    Filed: December 26, 2019
    Publication date: May 7, 2020
    Inventors: Shih-Wen Huang, Chia-Hui Lin, Shin-Yeu Tsai, Kai Hung Cheng
  • Patent number: 10629693
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer, a source/drain structure, a contact structure, a glue layer and a barrier layer. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The contact structure is positioned over the source/drain structure. The glue layer covers a bottom surface and a sidewall surface of the contact structure. The barrier layer encircles the sidewall surface of the contact structure. A bottom surface of the glue layer is exposed to the barrier layer.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wen Huang, Chung-Ting Ko, Hong-Hsien Ke, Chia-Hui Lin, Tai-Chun Huang
  • Patent number: 10590303
    Abstract: Disclosed herein are improved thermoplastic polyurethane compositions, articles, and related methods. These compositions include aliphatic thermoplastic polyurethanes having a hard segment content ranging from 57 percent to 80 percent by weight. The hard coat compositions have a Shore D hardness of at least 70 and can display an Elongation at Break test result at 25 degrees Celsius of at least 150 percent. These materials, when hardened, can serve decorative and/or protective functions while displaying both a high degree of elongation at moderate temperatures and high hardness.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: March 17, 2020
    Assignee: 3M Innovative Properties Company
    Inventors: Charlie C. Ho, Robert D. Hamann, Jeremy P. Gundale, Vijay Rajamani, Ken Egashira, Chia Hui Lin, Hsi Shou Kuo
  • Publication number: 20200075320
    Abstract: A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.
    Type: Application
    Filed: June 3, 2019
    Publication date: March 5, 2020
    Inventors: Dong-Sheng Li, Chia-Hui Lin, Kai Hung Cheng, Yao-Hsu Sun, Wen-Cheng Wu, Bo-Cyuan Lu, Sung-En Lin, Tai-Chun Huang
  • Publication number: 20200043799
    Abstract: An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls.
    Type: Application
    Filed: December 7, 2018
    Publication date: February 6, 2020
    Inventors: Chun-Yi Lee, Hong-Hsien Ke, Chung-Ting Ko, Chia-Hui Lin, Jr-Hung Li