Abstract: Disclosed herein are improved thermoplastic polyurethane compositions, articles, and related methods. These compositions include aliphatic thermoplastic polyurethanes having a hard segment content ranging from 57 percent to 80 percent by weight. The hard coat compositions have a Shore D hardness of at least 70 and can display an Elongation at Break test result at 25 degrees Celsius of at least 150 percent. These materials, when hardened, can serve decorative and/or protective functions while displaying both a high degree of elongation at moderate temperatures and high hardness.

Abstract: A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.

Abstract: An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls.

Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.

Abstract: Disclosed herein are composite fluorescent gold nanoclusters with high quantum yield, as well as methods for manufacturing the same. According to some embodiments, the composite fluorescent gold nanocluster includes a gold nanocluster and a capping layer that encapsulates at least a portion of the outer surface of the gold nanocluster. The capping layer includes a matrix made of a benzene-based compound, and multiple phosphine-based compounds distributed across the matrix.

Abstract: The present disclosure provides cell-free nucleic acid standards comprising genomic polynucleotides and methods of using cell-free nucleic acid standards comprising genomic polynucleotides for developing, optimizing, and validating cell-free nucleic acid assays.

Abstract: An electronic device and a tiling electronic apparatus are disclosed and include a base substrate, a first circuit layer and a plurality of light-emitting elements. The base substrate has a first surface and a second surface opposite to each other. The first circuit layer includes a first portion and a second portion. The first portion is disposed on the first surface of the base substrate, and the second portion is disposed on the second surface of the base substrate. The light-emitting elements are disposed on the first portion of the first circuit layer. At least one of the second surface of the base substrate and the first portion of the first circuit layer includes at least one microstructure.

Abstract: Semiconductor device structures and methods for forming the same are provided. A semiconductor device structure includes a gate structure over a semiconductor substrate. The gate structure includes a gate electrode layer and a gate dielectric layer covering a bottom surface and sidewalls of the gate electrode layer. The semiconductor device structure also includes spacer elements in contact with sidewalls of the gate structure and protruding from a top surface of the gate electrode layer. The semiconductor device structure also includes a first protection layer over the gate electrode layer and between the spacer elements. The semiconductor device structure also includes a dielectric layer over the first protection layer and between the spacer elements. A portion of the dielectric layer is between sidewalls of the spacer elements and sidewalls of the first protection layer.

Abstract: A method includes the steps of: monitoring status information of a blockchain system; determining whether the status information meets a blockchain branch condition; when the status information matches the blockchain branch condition, writing a branch instruction to a selected block of the blockchain, wherein the branch instruction is configured to enable the blockchain to form a plurality of branches, and divide a plurality of blockchain devices in the blockchain system into a plurality of groups to verify the branches in parallel; and obtaining a maximum transmission delay time in the group, and deciding a new one to generate blocks of the first branch according to the maximum transmission delay time.

Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.

Abstract: Disclosed embodiments facilitate wireless channel calibration, ranging, and direction finding, between networked devices. A method on a first station (STA) may comprise: broadcasting, at a first time, a first NDPA frame to a plurality of second STAs. The first NDPA frame may include a first bit indicating that one or more subsequent frames comprise ranging or angular information. After a Short Interval Frame Space (SIFS) time interval from the first time, a second frame may be broadcast. The second frame may be a Null Data Packet (NDP) frame. In response, a plurality of Compressed Beamforming (CBF) frames may be received at the first STA where each CBF frame may be received from a distinct corresponding second STA, and may include Channel Feedback Information field with information pertaining to communication channel between the first STA and the corresponding second STA. The communications may be encoded using Orthogonal Frequency Division Multiple Access.

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer, a source/drain structure, a contact structure, a glue layer and a barrier layer. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The contact structure is positioned over the source/drain structure. The glue layer covers a bottom surface and a sidewall surface of the contact structure. The barrier layer encircles the sidewall surface of the contact structure. A bottom surface of the glue layer is exposed to the barrier layer.

Abstract: Semiconductor device structures and methods for forming the same are provided. A method for forming a semiconductor device structure includes forming a gate structure over a semiconductor substrate. The method also includes forming spacer elements adjoining sidewalls of the gate structure. The method further includes forming a protection material layer over the gate structure. The formation of the protection material layer includes a substantial non-plasma process. In addition, the method includes depositing a dielectric material layer over the protection material layer. The deposition of the dielectric material layer includes a plasma-involved process.

Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.

Abstract: Semiconductor device structures and methods for forming the same are provided. A method for forming a semiconductor device structure includes forming a gate structure over a semiconductor substrate. The method also includes forming spacer elements adjoining sidewalls of the gate structure. The method further includes forming a protection material layer over the gate structure. The formation of the protection material layer includes a substantial non-plasma process. In addition, the method includes depositing a dielectric material layer over the protection material layer. The deposition of the dielectric material layer includes a plasma-involved process.

Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.

Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.

Abstract: Disclosed embodiments facilitate wireless channel calibration, ranging, and direction finding, between networked devices. A method on a first station (STA) may comprise: broadcasting, at a first time, a first NDPA frame to a plurality of second STAs. The first NDPA frame may include a first bit indicating that one or more subsequent frames comprise ranging or angular information. After a Short Interval Frame Space (SIFS) time interval from the first time, a second frame may be broadcast. The second frame may be a Null Data Packet (NDP) frame. In response, a plurality of Compressed Beamforming (CBF) frames may be received at the first STA where each CBF frame may be received from a distinct corresponding second STA, and may include Channel Feedback Information field with information pertaining to communication channel between the first STA and the corresponding second STA. The communications may be encoded using Orthogonal Frequency Division Multiple Access.

Abstract: Disclosed embodiments facilitate wireless channel calibration, including ranging and direction finding, between wirelessly networked devices. In some embodiments. a method on a first station (STA) may comprise: transmitting a first NDPA frame to one or more second stations (STAs), the first NDPA frame comprising a first bit indicating that one or more subsequent frames comprise ranging or angular information; and transmitting, after a Short Interval Frame Space (SIFS) time interval, a second frame. The second frame may be one of: a Null Data Packet az (NDP_az) frame with information about a time of transmission of the NDP_az frame, or a Null Data Packet (NDP) frame, or a Beam Refinement Protocol (BRP) frame. The first NDPA frame may be unicast, multicast, or broadcast.