Patents by Inventor Chia-Hung Lai

Chia-Hung Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interconnect structure and method for its fabricating
    Publication number: 20050173799
    Abstract: A method of fabricating an interconnect structure, including providing a semiconductor substrate having a first conductive layer thereon, and forming a dielectric layer overlying the semiconductor substrate and the first conductive layer. An opening is formed in the dielectric layer extending to the first conductive layer. A portion of the first conductive layer is removed through the opening to form a recess having a substantially curvilinear profile. The opening and the recess are filled with a second conductive layer.
    Type: Application
    Filed: February 5, 2004
    Publication date: August 11, 2005
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Juan-Jann Jou, Yu-Hua Lee, Chin-Tien Yang, Chia-Hung Lai, Connie Hsu, Mu-Yi Lin, Min Cao, Chia-Yu Ku, Yuh-Da Fan
  • Bond pad scheme for Cu process
    Publication number: 20050095836
    Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.
    Type: Application
    Filed: November 29, 2004
    Publication date: May 5, 2005
    Inventors: Chia-Hung Lai, Jiunn-Jyi Lin, Tzong-Sheng Chang, Min Cao, Huan-Chi Tseng, Yu-Hua Lee, Chin-Tien Yang
  • Bond pad scheme for Cu process
    Patent number: 6844626
    Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: January 18, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hung Lai, Jiunn-Jyi Lin, Tzong-Sheng Chang, Min Cao, Huan-Chi Tseng, Yu-Hua Lee, Chin-Tien Yang
  • BOND PAD SCHEME FOR CU PROCESS
    Publication number: 20040235223
    Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.
    Type: Application
    Filed: May 23, 2003
    Publication date: November 25, 2004
    Inventors: Chia-Hung Lai, Jiunn-Jyi Lin, Tzong-Sheng Chang, Min Cao, Huan-Chi Tseng, Yu-Hua Lee, Chin-Tien Yang
  • Laminated silicate glass layer etch stop method for fabricating microelectronic product
    Publication number: 20040074872
    Abstract: A method for fabricating a microelectronic fabrication employs an undoped silicate glass layer as an etch stop layer when etching a doped silicate glass layer with an anhydrous hydrofluoric acid etchant. The method is particularly useful for forming a patterned salicide blocking dielectric layer when fabricating a complementary metal oxide semiconductor device.
    Type: Application
    Filed: October 22, 2002
    Publication date: April 22, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ming Chen, Huan-Chi Tseng, Yu-Hua Lee, Dian-Hau Chen, Chia-Hung Lai, Kang-Min Kuo
  • Method of stripping photoresist from Al bonding pads that prevents corrosion
    Patent number: 6006764
    Abstract: The present invention provides a method of removing photoresist from a wafer surface having a bonding pad using a three step clean composed of (1) a wet cleaning the substrate, (2) a F-containing gas high temperature plasma treatment which prevents the corrosion of aluminum contact pad, and (3) completely striping the photoresist strip using an O.sub.2 dry ash. The invention eliminates metal bonding pad corrosion and the completely removes residual photoresist from keyholes.
    Type: Grant
    Filed: January 28, 1997
    Date of Patent: December 28, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Tao Chu, Ching-Wen Cho, Chia-Hung Lai, Chih-Chien Hung