Patents by Inventor Chia-Jung Chen

Chia-Jung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210124098
    Abstract: The present invention discloses a quantum-dot composite optical film comprising: a plurality of quantum dots dispersed in the optical film, wherein the plurality of quantum dots are capable of being water-resistant and oxygen-resistant; and a plurality of prisms, disposed over the quantum-dot layer.
    Type: Application
    Filed: October 22, 2020
    Publication date: April 29, 2021
    Inventors: Chia-Yeh Miu, Chia-Jung Chiang, Chien-Chih Lai, Lung-Pin Hsin, Yi-Long Tyan, Jeffrey Wu, Hui-Yong Chen
  • Publication number: 20210122972
    Abstract: The present invention discloses a quantum-dot film, wherein the quantum-dot film comprises a binder and a plurality of quantum dots dispersed in the binder, wherein the plurality of quantum dots are capable of being water-resistant and oxygen-resistant.
    Type: Application
    Filed: October 22, 2020
    Publication date: April 29, 2021
    Inventors: Chia-Yeh Miu, Ge-Wei Lin, Chia-Jung Chiang, Chien-Chih Lai, Lung-Pin Hsin, Yi-Long Tyan, Jeffrey Wu, Hui-Yong Chen, Ying-Yi Lu
  • Patent number: 10969991
    Abstract: A multi-chip package, a controlling method of the multi-chip package and a security chip are provided. The multi-chip package includes a memory chip and a security chip. The security chip is coupled between the memory chip and a host. The security chip includes a processing circuit. The processing circuit is for enabling a security path to input an input-output signal into the processing circuit for executing a security procedure and accessing the memory chip, if a command is received by the processing circuit and the command includes a security requirement.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: April 6, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chia-Jung Chen, Chin-Hung Chang, Ken-Hui Chen
  • Publication number: 20210057002
    Abstract: A memory device, including a secure command decoder implementing security logic configured to detect commands carrying an encrypted immediate data payload from a requesting host, authenticate the host as source of the command, decode the immediate data and perform a memory access command called for by a command portion of the decrypted immediate data upon the storage cells of the memory device using the non-command portion of the decrypted immediate data, as well as to encrypt any result from executing the command portion prior to returning the result to the requesting host, and an input/output interface for I/O data units supporting multiple hosts.
    Type: Application
    Filed: April 16, 2020
    Publication date: February 25, 2021
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chia-Jung CHEN, Chin-Hung CHANG, Ken-Hui CHEN
  • Publication number: 20210051020
    Abstract: A memory device can comprise a memory, and an interface to receive a memory command sequence. A message authentication code MAC is provided with the command sequence. Control circuits on the device include a command decoder to decode a received a command sequence and to execute an identified memory operation. A message authentication engine includes logic to compute a value of a message authentication code to be matched with the received message authentication code based on the received command sequence and a stored key. The device can store a plurality of keys associated with one or more memory zones in the memory. Logic on the device prevents completion of the memory operation identified by the command sequence if the value computed does not match the received message authentication code.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 18, 2021
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chia-Jung CHEN, Chin-Hung CHANG, Kuen-Long CHANG
  • Publication number: 20200242273
    Abstract: A memory chip comprises a first memory controller, a first data storage zone, a security unit and an address configuration unit. The first data storage zone is coupled to the first memory controller, and represented by a first physical address range. The security unit is coupled to the first memory controller. The address configuration unit is coupled to the first memory controller. The memory chip is configured to be coupled between a host controller and another memory chip. The another memory chip comprises a second data storage zone represented by a second physical address range. The address configuration unit records one or more relationships of a logical address range corresponding to the first physical address range and the second physical address range. The security unit is configured to encrypt and decrypt data in the first data storage zone and the second data storage zone.
    Type: Application
    Filed: December 24, 2019
    Publication date: July 30, 2020
    Inventors: Kuen-Long CHANG, Chia-Jung CHEN, Chin-Hung CHANG, Ken-Hui CHEN
  • Publication number: 20200192824
    Abstract: A security memory device coupled to a host includes: a normal region for storing normal data; a security region for storing security data; and a memory controller, coupled to the normal region and to the security region. In response to a first command which is issued from the host and indicates the security memory device to enter a security field, the memory controller allows the host to access the security region. In the security field, the memory controller performs at least one security command set on the security region. In response to a second command which is issued from the host and indicates the security memory device to exit the security field, the memory controller prohibits the host from accessing the security region.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 18, 2020
    Inventors: Yu-Chen WANG, Chia-Jung CHEN, Chin-Hung CHANG, Ken-Hui CHEN
  • Patent number: 10660212
    Abstract: The present disclosure provides an element submount and a method for manufacturing the same. The element submount includes a substrate, a first conductive heat-dissipating layer, a second conductive heat-dissipating layer, a first heat-dissipating layer and an element bonding layer. The substrate has opposite first and second surfaces. The first conductive heat-dissipating layer is formed on the first surface. The second conductive heat-dissipating layer is formed on the first surface and separated from the first conductive heat-dissipating layer. The first heat-dissipating layer is formed on the second surface. The element bonding layer is formed on the second conductive heat-dissipating layer. By electroplating and processing techniques, the edge of one or two sides of the element bonding layer exceeds an edge of the second conductive heat-dissipating layer and partially covers a side of the second conductive heat-dissipating layer.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: May 19, 2020
    Assignee: XSENSE TECHNOLOGY CORPORATION
    Inventors: Chen-Yu Li, Chia-Jung Chen, Yeu-Wen Huang, Chun-Chung Lin, Chih-Lung Lin
  • Publication number: 20200057575
    Abstract: A multi-chip package, a controlling method of the multi-chip package and a security chip are provided. The multi-chip package includes a memory chip and a security chip. The security chip is coupled between the memory chip and a host. The security chip includes a processing circuit. The processing circuit is for enabling a security path to input an input-output signal into the processing circuit for executing a security procedure and accessing the memory chip, if a command is received by the processing circuit and the command includes a security requirement.
    Type: Application
    Filed: August 15, 2018
    Publication date: February 20, 2020
    Inventors: Chia-Jung Chen, Chin-Hung Chang, Ken-Hui Chen
  • Publication number: 20190352187
    Abstract: The present disclosure provides a method for repairing defect of graphene, including: firstly introducing a composite fluid containing a reactive compound and a supercritical fluid to a reactor where the graphene powder has been placed, and impregnating the graphene powder with the composite fluid to passivate and repair the defect of graphene, wherein the reactive compound includes carbon, hydrogen, nitrogen, silicon or oxygen element; and separating the composite fluid from the graphene powder, simultaneously using molecular sieves to absorb the graphene from the composite fluid. The present disclosure further provides the graphene powder prepared by the method above. With the method of the present disclosure, it effectively reduces the ratio of the defect of the graphene, increases the content of the graphene, and has less-layer graphene with high thermal conductivity and electrical conductivity.
    Type: Application
    Filed: May 15, 2019
    Publication date: November 21, 2019
    Inventors: Zhen-Yu Li, Po-Min Tu, Chia-Jung Chen, Yeu-Wen Huang
  • Publication number: 20190124774
    Abstract: The present disclosure provides an element submount and a method for manufacturing the same. The element submount includes a substrate, a first conductive heat-dissipating layer, a second conductive heat-dissipating layer, a first heat-dissipating layer and an element bonding layer. The substrate has opposite first and second surfaces. The first conductive heat-dissipating layer is formed on the first surface. The second conductive heat-dissipating layer is formed on the first surface and separated from the first conductive heat-dissipating layer. The first heat-dissipating layer is formed on the second surface. The element bonding layer is formed on the second conductive heat-dissipating layer. By electroplating and processing techniques, the edge of one or two sides of the element bonding layer exceeds an edge of the second conductive heat-dissipating layer and partially covers a side of the second conductive heat-dissipating layer.
    Type: Application
    Filed: October 4, 2018
    Publication date: April 25, 2019
    Inventors: Chen-Yu Li, Chia-Jung Chen, Yeu-Wen Huang, Chun-Chung Lin, Chih-Lung Lin
  • Patent number: 10032511
    Abstract: For a memory array including a plurality of bit lines, and a set of write drivers having a number N members configured for connection in parallel to a selected set of N bit lines in the plurality of bit lines, write logic is coupled to the set of write drivers which enables a permissible number less than said number N of said members of the set of write drivers to apply a write pulse in parallel in a write operation. The write logic can dynamically assign permissible numbers to iterations in an iterative write sequence. A power source, such as charge pump circuitry, coupled to the set of write drivers can be utilized more efficiently in systems applying permissible bit write logic, enabling higher throughput or utilizing lower peak power.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: July 24, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung Hung, Chia-Jung Chen
  • Patent number: 9779810
    Abstract: A write pulse driver is provided. The write pulse driver includes a parameter storage, storing a set of parameters specifying characteristics of a write pulse, and driver circuitry configured to generate the write pulse on an output node, the write pulse having a leading edge, a trailing edge and an intermediate segment between the leading edge and the trailing edge, wherein the driver circuitry includes pulse shaping circuits that set shape characteristics of at least one of an amplitude, a duration and a slope of more than one of the leading edge, the trailing edge and the intermediate segment of the write pulse using the set of parameters.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: October 3, 2017
    Assignees: MACRONIX INTERNATIONAL CO., LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Jung Chen, Scott C. Lewis
  • Patent number: 9685228
    Abstract: A sensing method for a memory is provided. The memory includes: a memory cell; a reference circuit generating a reference voltage and a clamp voltage; and a current supplying circuit receiving the clamp voltage to develop a cell current passing through the memory cell to form a cell voltage, wherein the cell voltage is used for incorporating with the reference voltage to determine the information stored in the memory.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: June 20, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Tien-Yen Wang, Chun-Hsiung Hung, Chia-Jung Chen
  • Publication number: 20170076795
    Abstract: A write pulse driver is provided. The write pulse driver includes a parameter storage, storing a set of parameters specifying characteristics of a write pulse, and driver circuitry configured to generate the write pulse on an output node, the write pulse having a leading edge, a trailing edge and an intermediate segment between the leading edge and the trailing edge, wherein the driver circuitry includes pulse shaping circuits that set shape characteristics of at least one of an amplitude, a duration and a slope of more than one of the leading edge, the trailing edge and the intermediate segment of the write pulse using the set of parameters.
    Type: Application
    Filed: February 24, 2016
    Publication date: March 16, 2017
    Applicants: MACRONIX INTERNATIONAL CO., LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: CHIA-JUNG CHEN, SCOTT C. LEWIS
  • Patent number: 9507663
    Abstract: A memory device and an operation method thereof are provided, and the operation method of the memory device includes following steps. A programming operation is performed to write an original data into a first memory array in the memory device. The original data in the first memory array is verified, and whether to generate a write signal is determined according to a verification result. An error correction code is generated according to the original data, and the error correction code and a write address are stored temporarily in a buffer circuit of the memory device. When the write signal is generated, the error correction code and the write address in the buffer circuit are written into a second memory array in the memory device.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: November 29, 2016
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Hsin-Yi Ho, Hsiang-Lan Lung, Wei-Chih Chien, Tu-Shun Chen, Chia-Jung Chen
  • Publication number: 20160328288
    Abstract: A memory device and an operation method thereof are provided, and the operation method of the memory device includes following steps. A programming operation is performed to write an original data into a first memory array in the memory device. The original data in the first memory array is verified, and whether to generate a write signal is determined according to a verification result. An error correction code is generated according to the original data, and the error correction code and a write address are stored temporarily in a buffer circuit of the memory device. When the write signal is generated, the error correction code and the write address in the buffer circuit are written into a second memory array in the memory device.
    Type: Application
    Filed: May 4, 2015
    Publication date: November 10, 2016
    Inventors: Hsin-Yi Ho, Hsiang-Lan Lung, Wei-Chih Chien, Tu-Shun Chen, Chia-Jung Chen
  • Patent number: 9275695
    Abstract: A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit line groups are kept precharged.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: March 1, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chin-Hung Chang, Chia-Jung Chen, Su-Chueh Lo, Ken-Hui Chen, Kuen-Long Chang
  • Publication number: 20150302922
    Abstract: A sensing method for a memory is provided. The memory includes: a memory cell; a reference circuit generating a reference voltage and a clamp voltage; and a current supplying circuit receiving the clamp voltage to develop a cell current passing through the memory cell to form a cell voltage, wherein the cell voltage is used for incorporating with the reference voltage to determine the information stored in the memory.
    Type: Application
    Filed: June 23, 2015
    Publication date: October 22, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: TIEN-YEN WANG, CHUN-HSIUNG HUNG, CHIA-JUNG CHEN
  • Patent number: 9161465
    Abstract: In a quick-release fixing structure for an electronic equipment, the electronic equipment includes a plurality of holes and a snap slot, and the quick-release fixing structure includes a substrate, a turning element and a plurality of fixing elements. The substrate includes a plurality of grooves and a port, and each groove includes a first groove hole and a second groove hole interconnected to the first groove hole, and the second groove hole is greater than the first groove hole. The turning element is coupled to the substrate and includes a bump exposed from the port and snapped into the snap slot. Each fixing element is passed through each first groove hole and fixed to each hole. The turning element can be turned to push the electronic equipment to move each fixing element into each second groove hole, and separate the electronic equipment from the substrate.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: October 13, 2015
    Assignee: GRAND-TEK TECHNOLOGY CO., LTD.
    Inventors: Chia-Jung Chen, Yu-Wei Lin