Abstract: The present invention provides a seal ring structure, which comprises a seal ring member. The seal ring member includes a first ring opening on one side and a second ring opening on the other. A periphery of the first ring opening includes a plurality of leak grooves. When the seal ring member and the valve ball squeeze each other, the plurality of leak grooves can reduce the torque required to rotate the valve ball. A leak-groove length of the plurality of leak grooves is smaller than a seal-ring-member length of the seal ring member. The plurality of leak grooves do not penetrate the seal ring member for avoiding leakage of fluid.

Abstract: In a file sharing system, a key manager unit realizes a correspondence between the first user identifier and the first public key in response to a registration request of the first user, generates a first key material for encrypting the first file into a first encrypted file, and generates a first credential according to the first user identifier, the first file identifier, the first public key and the first key material after receiving an access-right claim request to the first file from the first user. A file storage unit stores the first encrypted file and the first credential. The first user uses the first user identifier, the first file identifier and the first private key to retrieve the first key material out of the first credential, and uses the first key material to decrypt the first encrypted file into the first file.

Abstract: A vanity mirror with lighting function includes: a mounting portion, connected to a vehicle sun visor; a movable portion which can move relatively to the mounting portion; a mirror located in the mounting portion or the movable portion; a power storage unit; a front-open sensing unit for determining whether the vanity mirror is in a front-open state or a folded state; a sensing circuit, wherein when the vanity mirror is in the front-open state, the power storage unit conducts electrical power to the sensing circuit; and a light source for providing lighting function, wherein in the front-open state, whether to emit light and intensity of the light is determined according to the sensing result of the sensing circuit.

Abstract: A system for detecting hardware Trojans in a computerized device includes a digital circuit having switching components operating pursuant to at least one clock frequency and positioned within an interrogation range of an incident carrier wave. A modulated backscatter response is reflected from the digital circuit upon arrival of the incident carrier wave in the presence of the switching operations. A detection device is positioned to receive the modulated backscatter response. A computer connected to the detection device identifies harmonics of a respective clock frequency of the digital circuit from the backscatter response and identifies characteristics of the harmonics indicating a presence or an absence of a hardware Trojan connected to the digital circuit.

Abstract: A semi-passive radio frequency identification (RFID) tag includes a digital circuit with switching components operating within an interrogation range of an incident carrier wave. A plurality of input connections and output connections direct data communications through the switching components within the digital circuit, and the data communications are subject to switching operations of the switching components between at least one of the input connections and at least one of the output connections. A backscatter response reflected from the digital circuit upon arrival of the incident carrier wave, wherein the backscatter response is a modulated backscatter response in the presence of the switching operations.

Abstract: A semi-passive radio frequency identification (RFID) tag includes a digital circuit with switching components operating within an interrogation range of an incident carrier wave. A plurality of input connections and output connections direct data communications through the switching components within the digital circuit, and the data communications are subject to switching operations of the switching components between at least one of the input connections and at least one of the output connections. A backscatter response reflected from the digital circuit upon arrival of the incident carrier wave, wherein the backscatter response is a modulated backscatter response in the presence of the switching operations.

Abstract: A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance.

Abstract: A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance.

Abstract: A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance.

Abstract: A method and system for integrally checking a chip layout dataset and a package substrate layout dataset for errors are disclosed. The package substrate layout dataset is converted from a first format into a second format in which the chip layout dataset is provided. The chip layout dataset of the second format is combined with the package substrate layout dataset of the second format into a combined dataset. The combined dataset is then checked for errors or design rule violations.

Abstract: Methods of supplying voltages to integrated circuits are provided. A high voltage VddH and/or a low voltage VddL can be supplied to a filler cell and routed to other cells. Each of the VddH and VddL is carried by one of a first voltage supply wire and a second voltage supply wire. A voltage routing wire routes desired voltage(s) to a filler cell. The first and the second voltage supply wires are preferably formed parallel to the voltage routing wire with their edges substantially aligned to the edges of the voltage routing wire. Vias are made to route the desire voltage. Also preferably, the first voltage supply wire is an M1 wire formed outside the filler cell while the second voltage supply wire is an M2 wire formed inside the filler cell.

Abstract: A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance.

Abstract: A method and system for integrally checking a chip layout dataset and a package substrate layout dataset for errors are disclosed. The package substrate layout dataset is converted from a first format into a second format in which the chip layout dataset is provided. The chip layout dataset of the second format is combined with the package substrate layout dataset of the second format into a combined dataset. The combined dataset is then checked for errors or design rule violations.

Abstract: An integrated circuit for routing of an electrical connection include a first metal layer having a first set of dummy conductive segments discretely arranged, and a second metal layer having a second set of dummy conductive segments discretely arranged. The segments of the first and second sets are interleaved with vertically overlapped areas for providing a predetermined link path between a selected first and a selected second nodes on two dummy conductive segments by selectively connecting a predetermined subset of the first and second dummy conductive segments through their vertically overlapped areas.

Abstract: An integrated circuit for routing of an electrical connection include a first metal layer having a first set of dummy conductive segments discretely arranged, and a second metal layer having a second set of dummy conductive segments discretely arranged. The segments of the first and second sets are interleaved with vertically overlapped areas for providing a predetermined link path between a selected first and a selected second nodes on two dummy conductive segments by selectively connecting a predetermined subset of the first and second dummy conductive segments through their vertically overlapped areas.

Abstract: A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance.

Abstract: A method for synthesizing a clock distribution system within an integrated circuit for compensating for clock skew within a global or top level clock distribution network begins with allocating at least one delaying circuit within each of functional circuits of the integrated circuit. An intra-functional clock distribution network is fabricated within each of the functional circuits. Once the intra-functional clock distribution network is fabricated, an inter-functional clock distribution network is constructed between each of the functional circuits. A clock skew for the inter-functional clock distribution network is determined. The clock skew is then compensated by inserting the delaying circuit at a terminal of the inter-function clock distribution network where each of the functional circuits is connected to the inter-functional clock distribution network.

Abstract: Methods of supplying voltages to integrated circuits are provided. A high voltage VddH and/or a low voltage VddL can be supplied to a filler cell and routed to other cells. Each of the VddH and VddL is carried by one of a first voltage supply wire and a second voltage supply wire. A voltage routing wire routes desired voltage(s) to a filler cell. The first and the second voltage supply wires are preferably formed parallel to the voltage routing wire with their edges substantially aligned to the edges of the voltage routing wire. Vias are made to route the desire voltage. Also preferably, the first voltage supply wire is an M1 wire formed outside the filler cell while the second voltage supply wire is an M2 wire formed inside the filler cell.

Abstract: A method for synthesizing a clock distribution system within an integrated circuit for compensating for clock skew within a global or top level clock distribution network begins with allocating at least one delaying circuit within each of functional circuits of the integrated circuit. An intra-functional clock distribution network is fabricated within each of the functional circuits. Once the intra-functional clock distribution network is fabricated, an inter-functional clock distribution network is constructed between each of the functional circuits. A clock skew for the inter-functional clock distribution network is determined. The clock skew is then compensated by inserting the delaying circuit at a terminal of the inter-function clock distribution network where each of the functional circuits is connected to the inter-functional clock distribution network.

Abstract: Flexible routing channels among vias is disclosed. A semiconductor device of one embodiment includes a number of metal layers, a number of dielectric layers, a number of via holes, and a number of routing channels. The metal layers are organized along a vertical axis. The dielectric layers are alternatively positioned relative to the metal layers. The via holes are situated within the dielectric layers and electrically connect a lower layer of the metal layers to an upper layer of the metal layers. The routing channels are situated within the metal layers and provide for electrical routing through the device along at least one of two horizontal axes of a horizontal plane perpendicular to the vertical axis.