Abstract: A method and system for the design of an electronic device adjusts the resistance and capacitance values employed in preliminary timing analysis during physical synthesis of the electronic device. The physical synthesis uses resistance and capacitance unit values to determine the listing of the component circuits. The resistance and capacitance unit values are calibrated by preliminarily placing the initially synthesized component circuits to create a listing describing physical locations of the component circuits within the electronic device. A preliminary routing of the interconnections is performed to create a listing describing a network of physical wire segments that form each interconnection of the component circuits. A timing analysis of the electronic device determines the delay created by the component circuit and the networks of physical wire segments.

Abstract: Flexible routing channels among vias is disclosed. A semiconductor device of one embodiment includes a number of metal layers, a number of dielectric layers, a number of via holes, and a number of routing channels. The metal layers are organized along a vertical axis. The dielectric layers are alternatively positioned relative to the metal layers. The via holes are situated within the dielectric layers and electrically connect a lower layer of the metal layers to an upper layer of the metal layers. The routing channels are situated within the metal layers and provide for electrical routing through the device along at least one of two horizontal axes of a horizontal plane perpendicular to the vertical axis.

Abstract: An output stage that reduces power or ground bouncing caused by a capacitive load while either a single or multiple outputs are switching at the same time. A first control means coupled to a power source generates first control signal to the gate terminal of a first MOS transistor in response to an input signal. A second control means coupled to ground generates a second control signal to the gate terminal of the second MOS transistor in response to the input signal. A first gate control means generates third and fourth control signals to the gate terminals of the first and second MOS transistor respectively, in response to the input signal, to turn on one of the first and second MOS transistors partially. A second gate control means generates fifth and sixth control signals to the gate terminals of the first and second MOS transistor respectively, in response to the input signal and the output signal, to turn on said one of the first and second MOS transistors entirely.

Abstract: A constant output circuit wherein outputs are not a function of deviations of reference voltage. More specifically, the outputs maintain their logic "1" and logic "0" values, even when there are reference voltage noise or fluctuation in the circuit. This constant output circuit having a logic "1" output node and a logic "0" output node comprises a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor. A logical inversion operation is performed between a first input node and a first output node of a logic circuit. The first input node is coupled to the logic "1" output node. The gate of said first PMOS transistor is coupled to the first output node of the logic circuit, the source to the power supply, and the drain to said logic "1" output node. The gate of said second PMOS transistor is coupled to the logic "1" output node, the source to the power supply, and the drain to said logic "1" output node.