Abstract: A circuit board assembly in a camera module for blocking unwanted light when images are captured includes a circuit board, a sensor, and an optical blocking body connecting the circuit board and the sensor. The circuit board includes a base board and a photomask. The photomask is arranged on a surface of the base board, the base board includes conductive circuit layers and dielectric layers, the conductive circuit layers and the dielectric layers are alternately arranged, the sensor being electronically connected to the conductive layers. The optical blocking body, the photomask, and the dielectric layers block ambient light entering the camera module other than through the lens assembly of the camera module.

Abstract: A method of manufacturing a snapback electrostatic discharge (ESD) protection circuit includes fabricating a first well in a substrate, the first well extending in a first direction, and having a first dopant type, fabricating a drain region of a transistor in the first well, the drain region having a second dopant type, fabricating a source region of the transistor in the first well, the source region extending in the first direction, having the second dopant type, and being separated from the drain region in a second direction, fabricating a second well in the first well, the second well extending in the first direction, having the second dopant type, and being adjacent to a portion of the drain region, and fabricating a gate region of the transistor, the gate region being between the drain region and the source region, and being over the first well and the substrate.

Abstract: An integrated circuit (IC) device includes a substrate, first and second semiconductor devices correspondingly in different first and second doped regions in the substrate. A gate of the first semiconductor device is electrically coupled to a source/drain of the second semiconductor device. The IC device further includes a first protection device configured as one of a first forward diode and a first reverse diode, and a second protection device configured as the other of the first forward diode and the first reverse diode. The first forward diode and the first reverse diode are electrically coupled in series between the substrate and a doped well. The doped well is in the first doped region and a source/drain of the first semiconductor device is in the doped well. Alternatively, the doped well is in the second doped region, and the source/drain of the second semiconductor device is in the doped well.

Abstract: A circuit includes a substrate, p-well regions over the substrate and including n- channel metal-oxide semiconductor field-effect transistors, n-well regions over the substrate and including p-channel metal-oxide semiconductor field-effect transistors, drain/source regions of protection metal-oxide semiconductor field-effect transistors, and at least one control circuit. First conductive connections connect selected drain/source regions to the p-well regions and the n-well regions, second conductive connections connect selected n-channel metal-oxide semiconductor field-effect transistors and p-channel metal-oxide semiconductor field-effect transistors to one another, and third conductive connections are configured to connect gates of the protection metal-oxide semiconductor field-effect transistors to the at least one control circuit.

Abstract: An electrostatic discharge (ESD) circuit includes a first ESD detection circuit, a first discharging circuit and a first ESD assist circuit. The first ESD detection circuit is coupled between a first node having a first voltage and a second node having a second voltage. The first discharging circuit includes a first transistor. The first transistor has a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to the first ESD detection circuit by a third node. The first drain is coupled to the first node. The first source and the first body terminal are coupled together at the second node. The first ESD assist circuit is coupled between the second and third node, and configured to clamp a third voltage of the third node at the second voltage during an ESD event at the first or second node.

Abstract: An IC device includes first and second CMOS structures positioned in n-type doped regions of a substrate, the first CMOS structure including a common gate terminal, first NMOS body and source contacts, and first PMOS body and source contacts, the second CMOS structure including a common drain terminal, second NMOS body and source contacts, and second PMOS body and source contacts. The IC device includes a first electrical connection from the common drain terminal to the common gate terminal, a clamp device including a diode, a second electrical connection from a cathode of the diode to the first PMOS body and source contacts, and a third electrical connection from an anode of the of the diode to the first NMOS body and source contacts, and entireties of each of the second and third electrical connections are positioned between the substrate and a third metal layer of the IC device.

Abstract: An ESD power clamp device includes an ESD detection circuit; a controlling circuit coupled with the ESD detection circuit; a field effect transistor (FET) coupled with the controlling circuit, and an impedance element coupled with the FET. The FET includes a drain terminal coupled with a first supply node; a gate terminal coupled with the controlling circuit; a source terminal coupled with a second supply node via the impedance element; and a bulk terminal coupled with second supply node.

Abstract: An electrostatic discharge (ESD) circuit includes an ESD detection circuit, a clamp circuit and an ESD assist circuit. The ESD detection circuit is coupled between a first and a second node. The first node has a first voltage. The second node has a second voltage. The clamp circuit includes a first transistor having a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to at least the ESD detection circuit by a third node. The first drain is coupled to the second node. The first source and the first body terminal are coupled together at the first node. The ESD assist circuit is coupled between the first node and the third node, and is configured to clamp a third voltage of the third node at the first voltage during an ESD event at the first node or the second node.

Abstract: A semiconductor fabrication facility (FAB) is provided. The FAB includes a group of processing tools. The FAB also includes a number of sampling tubes connecting the group of processing tools. In addition, the FAB includes a sampling station which includes a connection port, a valve manifold box and a controller. The valve manifold box is used for switching a gas sample from one of the processing tools to the connection port. The controller is sued for controlling the connection of the valve manifold box and the sampling tubes. The FAB further includes a metrology module. The metrology module is connected to the connection port of the sampling station and is used to perform a measurement of a parameter related to the gas sample.

Abstract: The present disclosure describes a method for forming a nitrogen-rich protective layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.

Abstract: An ESD power clamp device includes an ESD detection circuit; a controlling circuit coupled with the ESD detection circuit; a field effect transistor (FET) coupled with the controlling circuit, and an impedance element coupled with the FET. The FET includes a drain terminal coupled with a first supply node; a gate terminal coupled with the controlling circuit; a source terminal coupled with a second supply node via the impedance element; and a bulk terminal coupled with second supply node.

Abstract: An ESD power clamp device includes an ESD detection circuit; a controlling circuit coupled with the ESD detection circuit; a field effect transistor (FET) coupled with the controlling circuit, and an impedance element coupled with the FET. The FET includes a drain terminal coupled with a first supply node; a gate terminal coupled with the controlling circuit; a source terminal coupled with a second supply node via the impedance element; and a bulk terminal coupled with second supply node.

Abstract: Provided is a vaccine composition including a recombinant DNA vaccine against a pathogen. The recombinant DNA vaccine includes an expression cassette operably linked to a promoter, and the expression cassette encodes a non-structural protein of a Sindbis virus and an antigenic protein of the pathogen. Also provided is a method of producing a protective immune response against a pathogen in a subject in need thereof by administering the vaccine composition to the subject.

Abstract: A semiconductor fabrication facility (FAB) is provided. The FAB includes a group of processing tools. The FAB also includes a number of sampling tubes connecting the group of processing tools. In addition, the FAB includes a sampling station which includes a connection port, a valve manifold box and a controller. The valve manifold box is used for switching a gas sample from one of the processing tools to the connection port. The controller is sued for controlling the connection of the valve manifold box and the sampling tubes. The FAB further includes a metrology module. The metrology module is connected to the connection port of the sampling station and is used to perform a measurement of a parameter related to the gas sample.

Abstract: The present disclosure describes a method for forming a nitrogen-rich protective layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.

Abstract: A semiconductor fabrication facility (FAB) is provided. The FAB includes a number of processing tools. The FAB also includes a sampling station connected to the processing tools. In addition, the FAB includes a detection vehicle detachably connected to the sampling station and comprising a metrology module. When the detection vehicle is connected to the sampling station, a gas sample is delivered from one of the processing tools to the metrology module of the detection vehicle via the sampling station for performing a measurement of a parameter in related to the gas sample by the metrology module. In addition, the FAB includes a control system configured to issue a warning when the parameter in related to the gas sample from the one of the processing tools is out of a range of acceptable values associated with the one of the processing tools.

Abstract: An ESD power clamp device includes an ESD detection circuit; a controlling circuit coupled with the ESD detection circuit; a field effect transistor (FET) coupled with the controlling circuit, and an impedance element coupled with the FET. The FET includes a drain terminal coupled with a first supply node; a gate terminal coupled with the controlling circuit; a source terminal coupled with a second supply node via the impedance element; and a bulk terminal coupled with second supply node.

Abstract: An electrostatic discharge (ESD) circuit includes an ESD detection circuit, a clamp circuit and an ESD assist circuit. The ESD detection circuit is coupled between a first and a second node. The first node has a first voltage. The second node has a second voltage. The clamp circuit includes a first transistor having a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to at least the ESD detection circuit by a third node. The first drain is coupled to the second node. The first source and the first body terminal are coupled together at the first node. The ESD assist circuit is coupled between the first node and the third node, and is configured to clamp a third voltage of the third node at the first voltage during an ESD event at the first node or the second node.

Abstract: A semiconductor fabrication facility (FAB) is provided. The FAB includes a number of processing tools. The FAB also includes a sampling station connected to the processing tools. In addition, the FAB includes a detection vehicle detachably connected to the sampling station and comprising a metrology module. When the detection vehicle is connected to the sampling station, a gas sample is delivered from one of the processing tools to the metrology module of the detection vehicle via the sampling station for performing a measurement of a parameter in related to the gas sample by the metrology module. In addition, the FAB includes a control system configured to issue a warning when the parameter in related to the gas sample from the one of the processing tools is out of a range of acceptable values associated with the one of the processing tools.

Abstract: A cartridge for a bioreactor adapted for accommodating a plurality of objects includes a cartridge main body defining a plurality of spaced-apart accommodating slots for respectively accommodating the objects therein. The cartridge main body includes a retaining portion extending into at least one of the accommodating slots, and adapted to retain a corresponding one of the objects in a corresponding one of the accommodating slots. The retaining portion is pushable to move resiliently in the corresponding one of the accommodating slots.