Patents by Inventor Chia-Lin Hsu

Chia-Lin Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190279876
    Abstract: A method of manufacturing a semiconductor device includes exposing a material to a semi-aqueous etching solution. The semi-aqueous etching solution comprises a solvent which chelates with the material and acts as a catalyst between the etching driving force and the material. As such, the etching driving force may be used to remove the material.
    Type: Application
    Filed: May 30, 2019
    Publication date: September 12, 2019
    Inventors: Yao-Wen Hsu, Jian-Jou Lian, Neng-Jye Yang, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang, Li-Min Chen
  • Patent number: 10391608
    Abstract: A wafer polishing apparatus is described herein. The wafer polishing apparatus includes a polish module configured to apply air pressure to a first surface of a wafer while performing a polishing process on a second surface of the wafer. In some implementations, the polish module is further configured to perform a cleaning process and/or a drying process on the second surface of the wafer, such that the same wafer polishing apparatus is configured to perform the polishing process, the cleaning process, and/or the drying process. In some implementations, the polishing module is further configured to air seal edges of the wafer during the polishing process, the cleaning process, and/or the drying process.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: August 27, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hung Chen, Chia-Jung Hsu, Yi-An Lin
  • Patent number: 10395999
    Abstract: A method for monitoring fin removal includes providing a substrate having a first region with first fins extending along a first direction and a second region with second fins extending along a second direction, wherein the first direction is perpendicular to the second direction; forming a material layer on the substrate to cover the first fins and the second fins; identically patterning the first fins and the second fins using a first pattern and a second pattern respectively for simultaneously removing parts of the first and second fins, thereby forming first fin features in the first region and second fin features in the second region, wherein the first pattern has a first dimension along the second direction, the second pattern has a second dimension along the second direction, and the second dimension is equal to the first dimension; and monitoring the first fin features using the second fin features.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: August 27, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Hao Yang, En-Chiuan Liou, Hsiao-Lin Hsu, Tang-Chun Weng, Chia-Ching Lin, Yen-Pu Chen
  • Publication number: 20190258770
    Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai
  • Publication number: 20190222214
    Abstract: An oven controlled crystal oscillator consisting of heater-embedded ceramic package includes a substrate, a crystal package, a crystal blank, a metal lid, a first IC chip, and a cover lid. The crystal package is mounted on the substrate, and a central bottom of the crystal package is provided with the first IC chip. The crystal blank is mounted in the crystal package and sealed by the metal lid. The crystal package has an embedded heater layer establishing a symmetric thermal field with respect to the first IC chip and the crystal blank. Alternatively, a heater-embedded ceramic carrier substrate is arranged between the first IC chip and the crystal blank to establish a symmetric thermal field with respect to the first IC chip and the crystal blank. The cover lid is combined with the substrate to cover the crystal package and the metal lid.
    Type: Application
    Filed: March 25, 2019
    Publication date: July 18, 2019
    Inventors: CHIEN-WEI CHIANG, WAN-LIN HSIEH, CHIA-WEI CHEN, CHE-LUNG HSU, SHENG-HSIANG KAO, CHEN-YA WENG, CHIA-CHEN CHEN
  • Publication number: 20190183978
    Abstract: Long-acting agonistic analogs for CLR/RAMP receptors are provided that have an extended half-live in vivo.
    Type: Application
    Filed: July 24, 2018
    Publication date: June 20, 2019
    Inventors: Sheau Yu Hsu, Chia Lin Chang
  • Patent number: 10312106
    Abstract: A method of manufacturing a semiconductor device includes exposing a material to a semi-aqueous etching solution. The semi-aqueous etching solution comprises a solvent which chelates with the material and acts as a catalyst between the etching driving force and the material. As such, the etching driving force may be used to remove the material.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: June 4, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Hsu, Jian-Jou Lian, Neng-Jye Yang, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang, Li-Min Chen
  • Patent number: 10291236
    Abstract: An oven controlled crystal oscillator consisting of heater-embedded ceramic package includes a substrate, a crystal package, a crystal blank, a metal lid, a first IC chip, and a cover lid. The crystal package is mounted on the substrate, and a central bottom of the crystal package is provided with the first IC chip. The crystal blank is mounted in the crystal package and sealed by the metal lid. The crystal package has an embedded heater layer establishing a symmetric thermal field with respect to the first IC chip and the crystal blank. Alternatively, a heater-embedded ceramic carrier substrate is arranged between the first IC chip and the crystal blank to establish a symmetric thermal field with respect to the first IC chip and the crystal blank. The cover lid is combined with the substrate to cover the crystal package and the metal lid.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: May 14, 2019
    Assignee: TXC Corporation
    Inventors: Chien-Wei Chiang, Wan-Lin Hsieh, Chia-Wei Chen, Che-Lung Hsu, Sheng-Hsiang Kao, Chen-Ya Weng, Chia-Chen Chen
  • Patent number: 10276432
    Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Patent number: 10263088
    Abstract: Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Publication number: 20190109044
    Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.
    Type: Application
    Filed: December 11, 2018
    Publication date: April 11, 2019
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Publication number: 20190067117
    Abstract: A method of forming a semiconductor device includes forming a gate dielectric layer on a substrate; forming a barrier layer over the gate dielectric layer; treating the barrier layer to roughen an outer surface of the barrier layer, resulting in a treated barrier layer; and forming a metal layer over the treated barrier layer.
    Type: Application
    Filed: August 13, 2018
    Publication date: February 28, 2019
    Inventors: Yen-Ting Chen, Chia-Lin Hsu
  • Patent number: 10079174
    Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: September 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Patent number: 10049940
    Abstract: A method of forming a semiconductor device includes receiving a structure having a substrate, a gate trench over the substrate, and a dielectric layer over the substrate and surrounding the gate trench. The method further includes forming a gate dielectric layer in the gate trench, forming a barrier layer in the gate trench and over the gate dielectric layer, and treating the barrier layer to roughen an outer surface of the barrier layer, resulting in a treated barrier layer. The method further includes forming an n-type work function metal layer over the treated barrier layer.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Ting Chen, Chia-Lin Hsu
  • Publication number: 20180144978
    Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.
    Type: Application
    Filed: January 2, 2018
    Publication date: May 24, 2018
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Publication number: 20180145140
    Abstract: Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.
    Type: Application
    Filed: January 2, 2018
    Publication date: May 24, 2018
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Patent number: 9923095
    Abstract: The present invention provides a non-planar FET and a method of manufacturing the same. The non-planar FET includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: March 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Chia-Lin Hsu
  • Patent number: 9859390
    Abstract: Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Publication number: 20170338318
    Abstract: Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.
    Type: Application
    Filed: April 11, 2017
    Publication date: November 23, 2017
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Publication number: 20170250279
    Abstract: A fin field effect transistor (FinFET) is provided. The FinFET includes a substrate, a gate stack, and a filter layer, and strain layers. The substrate has a semiconductor fin. The gate stack is disposed across the semiconductor fin. The gate stack includes a gate dielectric layer, a work function layer and a metal filling layer. The gate dielectric layer is disposed on the semiconductor fin. The work function layer is disposed on the gate dielectric layer. The metal filling layer is over the work function layer. The filter layer is disposed between the work function layer and the metal filling layer to prevent or decrease penetration of diffusion atoms. The strain layers are beside the gate stack. A material of the filter layer is different from a material of the work function layer and a material of the metal filling layer.
    Type: Application
    Filed: February 25, 2016
    Publication date: August 31, 2017
    Inventors: Cheng-Chang Wei, Chia-Lin Hsu, Hsien-Ming Lee, Ji-Cheng Chen