Abstract: An ESD power clamp device includes an ESD detection circuit; a controlling circuit coupled with the ESD detection circuit; a field effect transistor (FET) coupled with the controlling circuit, and an impedance element coupled with the FET. The FET includes a drain terminal coupled with a first supply node; a gate terminal coupled with the controlling circuit; a source terminal coupled with a second supply node via the impedance element; and a bulk terminal coupled with second supply node.

Abstract: Provided is a vaccine composition including a recombinant DNA vaccine against a pathogen. The recombinant DNA vaccine includes an expression cassette operably linked to a promoter, and the expression cassette encodes a non-structural protein of a Sindbis virus and an antigenic protein of the pathogen. Also provided is a method of producing a protective immune response against a pathogen in a subject in need thereof by administering the vaccine composition to the subject.

Abstract: A semiconductor fabrication facility (FAB) is provided. The FAB includes a group of processing tools. The FAB also includes a number of sampling tubes connecting the group of processing tools. In addition, the FAB includes a sampling station which includes a connection port, a valve manifold box and a controller. The valve manifold box is used for switching a gas sample from one of the processing tools to the connection port. The controller is sued for controlling the connection of the valve manifold box and the sampling tubes. The FAB further includes a metrology module. The metrology module is connected to the connection port of the sampling station and is used to perform a measurement of a parameter related to the gas sample.

Abstract: The present disclosure describes a method for forming a nitrogen-rich protective layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.

Abstract: A semiconductor fabrication facility (FAB) is provided. The FAB includes a number of processing tools. The FAB also includes a sampling station connected to the processing tools. In addition, the FAB includes a detection vehicle detachably connected to the sampling station and comprising a metrology module. When the detection vehicle is connected to the sampling station, a gas sample is delivered from one of the processing tools to the metrology module of the detection vehicle via the sampling station for performing a measurement of a parameter in related to the gas sample by the metrology module. In addition, the FAB includes a control system configured to issue a warning when the parameter in related to the gas sample from the one of the processing tools is out of a range of acceptable values associated with the one of the processing tools.

Abstract: An ESD power clamp device includes an ESD detection circuit; a controlling circuit coupled with the ESD detection circuit; a field effect transistor (FET) coupled with the controlling circuit, and an impedance element coupled with the FET. The FET includes a drain terminal coupled with a first supply node; a gate terminal coupled with the controlling circuit; a source terminal coupled with a second supply node via the impedance element; and a bulk terminal coupled with second supply node.

Abstract: An electrostatic discharge (ESD) circuit includes an ESD detection circuit, a clamp circuit and an ESD assist circuit. The ESD detection circuit is coupled between a first and a second node. The first node has a first voltage. The second node has a second voltage. The clamp circuit includes a first transistor having a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to at least the ESD detection circuit by a third node. The first drain is coupled to the second node. The first source and the first body terminal are coupled together at the first node. The ESD assist circuit is coupled between the first node and the third node, and is configured to clamp a third voltage of the third node at the first voltage during an ESD event at the first node or the second node.

Abstract: A semiconductor fabrication facility (FAB) is provided. The FAB includes a number of processing tools. The FAB also includes a sampling station connected to the processing tools. In addition, the FAB includes a detection vehicle detachably connected to the sampling station and comprising a metrology module. When the detection vehicle is connected to the sampling station, a gas sample is delivered from one of the processing tools to the metrology module of the detection vehicle via the sampling station for performing a measurement of a parameter in related to the gas sample by the metrology module. In addition, the FAB includes a control system configured to issue a warning when the parameter in related to the gas sample from the one of the processing tools is out of a range of acceptable values associated with the one of the processing tools.

Abstract: A cartridge for a bioreactor adapted for accommodating a plurality of objects includes a cartridge main body defining a plurality of spaced-apart accommodating slots for respectively accommodating the objects therein. The cartridge main body includes a retaining portion extending into at least one of the accommodating slots, and adapted to retain a corresponding one of the objects in a corresponding one of the accommodating slots. The retaining portion is pushable to move resiliently in the corresponding one of the accommodating slots.

Abstract: A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor is disposed on the substrate within a first region and includes a first gate electrode. The first gate electrode includes a first filter layer between and in contact with a first conductive layer and a second conductive layer. The second transistor is disposed on the substrate within a second region and includes a second gate electrode. The second gate electrode includes a second filter layer between and in contact with a third conductive layer and a fourth conductive layer. The first transistor and the second transistor have a same conductive type, a first threshold voltage of the first transistor is lower than a second threshold voltage of the second transistor, and a first thickness of the first filter layer is larger than a second thickness of the second filter layer.

Abstract: A snapback electrostatic discharge (ESD) protection circuit includes a first well in a substrate, a drain region of a transistor, a source region of the transistor, a gate region of the transistor, and a second well embedded in the first well. The first well has a first dopant type. The drain region is in the first well, and has a second dopant type different from the first dopant type. The source region is in the first well, has the second dopant type, and is separated from the drain region in a first direction. The gate region is over the first well and the substrate. The second well is embedded in the first well, and is adjacent to a portion of the drain region. The second well has the second dopant type.

Abstract: The present disclosure describes a method for forming a capping layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.

Abstract: Metal gate formation methods are disclosed herein for providing metal gates with low work function to enhance semiconductor field effect transistor performance. An exemplary method includes forming a gate dielectric layer on a substrate and a barrier layer over the gate dielectric layer. An outer surface of the barrier layer is treated to increase its roughness. After the outer surface of the barrier layer is roughened, a metal layer is deposited over the barrier layer.

Abstract: A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor is disposed on the substrate within a first region and includes a first gate electrode. The first gate electrode includes a first filter layer between and in contact with a first conductive layer and a second conductive layer. The second transistor is disposed on the substrate within a second region and includes a second gate electrode. The second gate electrode includes a second filter layer between and in contact with a third conductive layer and a fourth conductive layer. The first transistor and the second transistor have a same conductive type, a first threshold voltage of the first transistor is lower than a second threshold voltage of the second transistor, and a first thickness of the first filter layer is larger than a second thickness of the second filter layer.

Abstract: A fin field effect transistor (FinFET) is provided. The FinFET includes a substrate, a gate stack, and a filter layer, and strain layers. The substrate has a semiconductor fin. The gate stack is disposed across the semiconductor fin. The gate stack includes a gate dielectric layer, a work function layer and a metal filling layer. The gate dielectric layer is disposed on the semiconductor fin. The work function layer is disposed on the gate dielectric layer. The metal filling layer is over the work function layer. The filter layer is disposed between the work function layer and the metal filling layer to prevent or decrease penetration of diffusion atoms. The strain layers are beside the gate stack. A material of the filter layer is different from a material of the work function layer and a material of the metal filling layer.

Abstract: A method of forming a semiconductor device includes forming a gate dielectric layer on a substrate; forming a barrier layer over the gate dielectric layer; treating the barrier layer to roughen an outer surface of the barrier layer, resulting in a treated barrier layer; and forming a metal layer over the treated barrier layer.

Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.

Abstract: A method of forming a semiconductor device includes forming a gate dielectric layer on a substrate; forming a barrier layer over the gate dielectric layer; treating the barrier layer to roughen an outer surface of the barrier layer, resulting in a treated barrier layer; and forming a metal layer over the treated barrier layer.

Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.

Abstract: Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.