Abstract: The present invention related to a CMP equipment, compatible with the existing manufacture processes. The CMP equipment of the present invention employs strip polishing platens that can be smaller than the wafer size, so that the layout is compact and the space is effectively utilized, leading to high throughput and efficient production management. The present invention provides a CMP equipment that offers greater flexibility in performing CMP for different fabrication processes through the choices of various polishing pads and/or polishing slurry.

Abstract: A chemical mechanical polishing (CMP) machine has a polish platen, having at least a first ring-shaped region and a second ring-shaped region. A control system for in-situ feeding back a polish profile of the CMP machine has at least a first sensor and a second sensor, respectively installed in the first and the second ring-shaped regions, and a control unit electrically connected to the first sensor and the second sensor for comparing the polish rates of portions of the wafer over the first and the second ring-shaped regions, respectively, according to signals of the first and the second sensors, and adjusting amounts of a slurry supplied by first and second slurry pump valves, corresponding to the first and second ring-shaped regions, according to a predetermined process, or adjusting forces loaded to the first and second regions of the wafer according to the predetermined process.

Abstract: A method of removing contaminants from a silicon wafer after chemical-mechanical polishing (CMP). After a copper chemical-mechanical polishing and a subsequent barrier chemical-mechanical polishing operation, an aqueous solution of ozone in de-ionized water is applied to clean the silicon wafer so that contaminants on the wafer are removed. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after copper and barrier CMP and then the wafer is cleaned using a chemical solution or de-ionized water. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after both copper-CMP and barrier-CMP and then the wafer is cleaned using a chemical solution or de-ionized water.

Abstract: A method of removing contaminants from a silicon wafer after chemical-mechanical polishing (CMP). After a copper chemical-mechanical polishing and a subsequent barrier chemical-mechanical polishing operation, an aqueous solution of ozone in de-ionized water is applied to clean the silicon wafer so that contaminants on the wafer are removed. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after copper and barrier CMP and then the wafer is cleaned using a chemical solution or de-ionized water. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after both copper-CMP and barrier-CMP and then the wafer is cleaned using a chemical solution or de-ionized water.

Abstract: The present invention related to a CMP equipment, compatible with the existing manufacture processes. The CMP equipment of the present invention employs strip polishing platens that can be smaller than the wafer size, so that the layout is compact and the space is effectively utilized, leading to high throughput and efficient production management. The present invention provides a CMP equipment that offers greater flexibility in performing CMP for different fabrication processes through the choices of various polishing pads and/or polishing slurry.

Abstract: A wafer carrier assembly for a chemical mechanical polishing apparatus and a polishing method using the same are provided. The present wafer carrier assembly comprises a first plate, a second plate and a flexible membrane. The first plate has a plurality of protrusions formed on a bottom surface thereof and the second plate has a plurality of apertures passing through. Each of the protrusions is matched with one of the apertures to enable the first plate and the second plate to detachably combine together. The flexible membrane is positioned under the second plate and contacts it. A surface of the flexible membrane opposite to the surface of the flexible membrane contacting the second plate provides a wafer-receiving surface.

Abstract: A method for planarization of a semiconductor wafer with a high selectivity is describe. The semiconductor wafer has a hard mask, a stop layer disposed on the hard mask, and a barrier layer disposed on the stop layer. The method includes performing a chemical mechanical polishing (CMP) process on the barrier layer so as to expose the stop layer, and removing the stop layer. The polishing selectivity of the barrier layer relative to the stop layer is greater than 50. Since the material of stop layer is different from the material of barrier layer, the high selectivity is easily achieved. Thus, the surface of semiconductor wafer can be highly planarized.

Abstract: A method for fabricating a vertical three-dimensional metal-insulator-metal capacitor (MIM capacitor) structure is disclosed. The present invention utilized a vertical three-dimensional MIM capacitor structure on the substrate to decrease the structure area of the MIM capacitor in logic integrated circuit and integration for copper dual damascene process at an identical capacitance on a chip; therefore, the capacitance density of the vertical three-dimensional capacitor can be increased. Furthermore, the present invention is provided a method for fabricating the vertical three-dimensional MIM capacitor structure that compatible with the fabrication of the copper dual damascene structure such that the number of the photomask during the fabrication process can be reduced.

Abstract: A method of fabricating a high-density capacitor. At least one first trench is formed in a dielectric layer positioned on a semiconductor substrate. A first liner layer and a first conductive layer are formed on the semiconductor substrate followed by a first planarization process. At least one second trench having a joint side wall with the first trench is formed in the dielectric layer. A capacitor dielectric layer, a second liner layer, and a second conductive layer are formed on the semiconductor substrate followed by a second planarization process. The surfaces of the first conductive layer and the second conductive layer are then exposed to form a high-density capacitor having a three-dimensional structure.

Abstract: A wafer carrier assembly for a chemical mechanical polishing apparatus and a polishing method using the same are provided. The present wafer carrier assembly comprises a first plate, a second plate and a flexible membrane. The first plate has a plurality of protrusions formed on a bottom surface thereof and the second plate has a plurality of apertures passing through. Each of the protrusions is matched with one of the apertures to enable the first plate and the second plate to detachably combine together. The flexible membrane is positioned under the second plate and contacts it. A surface of the flexible membrane opposite to the surface of the flexible membrane contacting the second plate provides a wafer-receiving surface.

Abstract: A method for planarization of a semiconductor wafer with a high selectivity is described. The semiconductor wafer has a hard mask, a stop layer disposed on the hard mask, and a barrier layer disposed on the stop layer. The method includes performing a chemical mechanical polishing (CMP) process on the barrier layer so as to expose the stop layer, and removing the stop layer. The polishing selectivity of the barrier layer relative to the stop layer is greater than 50. Since the material of stop layer is different from the material of barrier layer, the high selectivity is easily achieved. Thus, the surface of semiconductor wafer can be highly planarized.

Abstract: A chemical-mechanical polishing method for polishing a copper oxide layer and a copper layer. The copper oxide layer above the copper layer is first polished using an aqueous solution having a high concentration of polishing particles/chelating agent. The copper layer is then polished using a polishing slurry having a low concentration of polishing particles/chelating agent or the polishing slurry free of polishing particles/chelating agent. Alternatively, the copper oxide layer is polished using a mixture of the aqueous solution and the polishing slurry. After the copper oxide layer is removed, the copper layer is polished using the polishing slurry alone.

Abstract: A method for fabricating a vertical three-dimensional metal-insulator-metal capacitor (MIM capacitor) structure is disclosed. The present invention utilized a vertical three-dimensional MIM capacitor structure on the substrate to decrease the structure area of the MIM capacitor in logic integrated circuit and integration for copper dual damascene process at an identical capacitance on a chip; therefore, the capacitance density of the vertical three-dimensional capacitor can be increased. Furthermore, the present invention is provided a method for fabricating the vertical three-dimensional MIM capacitor structure that compatible with the fabrication of the copper dual damascene structure such that the number of the photomask during the fabrication process can be reduced.

Abstract: This invention relates to a method of forming a dual damascene via, in particular to a method of forming a dual damascene via by using a metal hard mask layer. The present invention uses a metal layer to be a hard mask layer to make the surface of the isolation layer become a level and smooth surface and not become a rounding convex and to prevent the via being connected with others vias to cause the leakage defects after forming the shape of the via.

Abstract: A slurry composition for chemical mechanical polishing (CMP) is provided. The slurry has a component of abrasives, such as alumina, silica, ceria, etc, an aqueous ozone with determined concentration, and an additive. A pH value of the slurry composition is between 1 and 10.

Abstract: A chemical mechanical polishing (CMP) machine has a polish platen, having at least a first ring-shaped region and a second ring-shaped region. A control system for in-situ feeding back a polish profile of the CMP machine has at least a first sensor and a second sensor, respectively installed in the first and the second ring-shaped regions, and a control unit electrically connected to the first sensor and the second sensor for comparing the polish rates of portions of the wafer over the first and the second ring-shaped regions, respectively, according to signals of the first and the second sensors, and adjusting amounts of a slurry supplied by first and second slurry pump valves, corresponding to the first and second ring-shaped regions, according to a predetermined process, or adjusting forces loaded to the first and second regions of the wafer according to the predetermined process.

Abstract: An apparatus of a polishing pad conditioner and a method thereof, wherein the apparatus comprises a high-pressure water pipe for transmitting water. The high-pressure pipe is connected to an end of an ultrasonic oscillator, and another end of the ultrasonic oscillator is connected to a water tank. A spraying structure located above the water tank ejects water in the form of a water knife. The ultrasonic oscillator provides energy to the high-pressure water and the water knife is utilized to clean residue off the polishing pad. The polishing pad conditioner moves in an opposite direction from that of the polishing pad to allow the water knife of the polishing pad conditioner to clean the entire surface area of the polishing pad.

Abstract: The present invention provides a method of reducing dishing and erosion of a conductive structure in the process of chemical mechanical polishing. The method comprises providing a dielectric layer having at least a via hole thereon. A barrier layer is formed on the dielectric layer and the via hole. A conductive layer, such as copper layer, is formed on the barrier layer and filled into the via hole to form the conductive structure. The partial conductive layer is removed to expose the partial barrier layer. The exposed barrier layer and the conductive structure are polished. The polishing step is implemented by using a reagent whereby a metallic compound is formed on the conductive structure for protecting the conductive structure against dishing and erosion.

Abstract: In accordance with the present invention, a system for planarizing a substrate in fabricating semiconductor devices is provided. The system comprises at least two different types of polishing module which are arranged in an arbitrary sequence beginning with a first polishing module and ending with a last polishing module, means for transferring the substrate between the polishing modules, a load station, and an unload station. The load station is for loading the transferring means with the substrate prior to starting polishing at the first polishing module, and the unload station is for unloading the substrate from the transferring means after ending polishing at the last polishing module. A method for planarizing a substrate in fabricating semiconductor devices by using a polishing system is also provided.

Abstract: In accordance with the present invention, a system for planarizing a substrate in fabricating semiconductor devices is provided. The system comprises at least two different types of polishing module which are arranged in an arbitrary sequence beginning with a first polishing module and ending with a last polishing module, means for transferring the substrate between the polishing modules, a load station, and an unload station. The load station is for loading the transferring means with the substrate prior to starting polishing at the first polishing module, and the unload station is for unloading the substrate from the transferring means after ending polishing at the last polishing module. A method for planarizing a substrate in fabricating semiconductor devices by using a polishing system is also provided.