Abstract: An electro-chemical plating system includes an upper rotor assembly for receiving and holding a wafer; an electroplating reactor vessel for containing plating solution in which the wafer is immersed; an anode array including a plurality of concentric anode segments provided inside the electroplating reactor vessel; a power supply system including power supply subunits for controlling electrical potentials of the anode segments, respectively; and a plurality of sensor devices mounted inside the upper rotor assembly, wherein the sensor devices are substantially arranged in corresponding to the anode segments, and during operation, the plurality of sensor devices are utilized for in-situ feeding back a deposition profile to a control unit in real time.

Abstract: A planarization process for a pre-damascene structure is described, wherein the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask. A first CMP step is conducted using a first slurry to remove the second material layer outside the damascene opening. A second CMP step is conducted using a second slurry to remove the metal hard mask.

Abstract: A method of removing contaminants from a silicon wafer after chemical-mechanical polishing (CMP). After a copper chemical-mechanical polishing and a subsequent barrier chemical-mechanical polishing operation, an aqueous solution of ozone in de-ionized water is applied to clean the silicon wafer so that contaminants on the wafer are removed. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after copper and barrier CMP and then the wafer is cleaned using a chemical solution or de-ionized water. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after both copper-CMP and barrier-CMP and then the wafer is cleaned using a chemical solution or de-ionized water.

Abstract: A method for remote server login is disclosed, in which the method using a second pathway for remote server login is adopted. When a user requires to login to the remote server, he receives a virtual account by entering a user account. The virtual account and a password are then entered into the remote server using another device. After the remote server successfully authenticates the virtual account and the password, the user is authorized by the remote server to login. As a result, the objective for providing secure user login for remote server is achieved.

Abstract: A method of manufacturing a conductive layer is described. A substrate having a dielectric layer thereon is provided. The dielectric layer has a patterned structure and the patterned structure exposes a portion of the conductive layer. The surface of the substrate is cleaned in a first cleaning step and a cap layer is formed over the exposed portion of the conductive layer. Thereafter, the surface of the substrate is cleaned again in a second cleaning step to remove the residual cap layer on the surface of the dielectric layer. Finally, a dry cleaning step is performed to clean and dry the surface of the substrate.

Abstract: A process for electroless plating a metal cap barrier on a substrate is disclosed. Copper metallization is formed on the substrate such that the substrate has an exposed top surface of a copper line. The exposed top surface of the copper line is pre-cleaned. The pre-cleaned exposed top surface of the copper line is exposed to an activation solution. The exposed top surface of the copper line of the substrate is then in-situ annealed in an vapor ambient containing a flow of alcohol and carrier gas at a temperature less than 400° C. The metal cap barrier is selectively deposited onto the exposed top surface of the copper line by performing electroless plating.

Abstract: A method for manufacturing a metal plug is described. A substrate with an opening is provided. Then, a barrier layer is formed on a surface of the opening. Thereafter, a metallic layer is formed over the substrate so that the opening is also filled. Next, a planarization process is performed to remove the metallic layer outside the opening. One main feature of the present invention is the performance of at least a high temperature treatment after the metallic layer is formed. Due to the high temperature treatment, internal stress between different layers is released.

Abstract: A planarization process for a pre-damascene structure is described, wherein the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask. A first CMP step is conducted using a first slurry to remove the second material layer outside the damascene opening. A second CMP step is conducted using a second slurry to remove the metal hard mask.

Abstract: A method of forming a plug is provided. First, a substrate comprising at least a dielectric layer is provided, and a patterned hard mask is formed on the dielectric layer to define a position of at least a plug hole. Subsequently, the dielectric layer is etched for forming the plug hole. A barrier layer and a conductive layer are formed on the substrate, and the plug hole is filled by the conductive layer. Thereafter, first, second, and third chemical mechanical polishing processes are performed in turn. Finally, a fourth chemical mechanical polishing process is performed to remove portions of the conductive layer.

Abstract: A method for improving edge peeling defect is disclosed in this invention. According to this invention, a wafer can be kept from the edge peeling defect of the prior art by introducing a step for removing the weakly adhesive films and the metal structures at the wafer edge after forming a metal interconnect layer on the wafer. Thus, this invention can raise the yield of semiconductor manufacturing, and reduce the pollution chance of the chamber of the semiconductor manufacture.

Abstract: An electro-chemical plating system includes an upper rotor assembly for receiving and holding a wafer; an electroplating reactor vessel for containing plating solution in which the wafer is immersed; an anode array including a plurality of concentric anode segments provided inside the electroplating reactor vessel; a power supply system including power supply subunits for controlling electrical potentials of the anode segments, respectively; and a plurality of sensor devices mounted inside the upper rotor assembly, wherein the sensor devices are substantially arranged in corresponding to the anode segments, and during operation, the plurality of sensor devices are utilized for in-situ feeding back a deposition profile to a control unit in real time.

Abstract: A method of fabricating a barrier layer is described. A material layer having an opening formed therein is provided. Then, the material layer is disposed inside a physical vapor deposition chamber and a first deposition process is performed to form a first barrier layer on the surface of the opening. The first deposition process includes turning on a plasma source and turning off the plasma source. The turning on of the plasma source and the turning off of the plasma source are separated from each other by an interval less than 2 seconds. Thereafter, the first deposition process is repeated several times to form a second barrier layer comprising a plurality of first barrier layers.

Abstract: The method of metallization in the fabrication of an integrated circuit device comprises the steps as follows. First, a dielectric layer overlying a semiconductor substrate is provided. The dielectric layer has a top surface and a plurality of openings. Next, a metal layer is formed on the dielectric layer and filling the openings. Subsequently, a first removing process is performed to partially removing the metal layer. A first annealing process is performed on the metal layer. Finally, a second removing process is performed to remove the metal layer completely to leave the metal layer only within the openings.

Abstract: A high throughput chemical mechanical polishing process is disclosed. A substrate having thereon a top bulk metal layer and a lower barrier layer is prepared. The top bulk metal layer is polished at a substantial constant removal rate to expose the barrier layer by utilizing a first platen and first slurry being selective to the barrier layer. The exposed barrier layer is then polished by using a second platen and second slurry. The first slurry has a copper to barrier polishing selectivity of greater than 30.

Abstract: A first substrate and second substrate both having thereon a top bulk metal layer and a lower barrier layer are prepared. The first substrate is first loaded onto a first platen of a CMP tool, and then an upper portion of the top bulk metal layer of the first substrate is removed by first platen and first slurry. The first substrate is then transferred to a second platen having second slurry. The second substrate is loaded onto the first platen. Simultaneously, the remaining top bulk metal layer of the first substrate and an upper portion of top bulk metal layer of the second substrate are removed at substantially the same copper removal rate until the lower barrier layer of the first substrate is exposed. The first substrate is transferred to a third platen having third slurry for polishing the exposed barrier layer.

Abstract: A high throughput chemical mechanical polishing process is disclosed. A substrate having thereon a top bulk metal layer and a lower barrier layer is prepared. The top bulk metal layer is polished at a substantial constant removal rate to expose the barrier layer by utilizing a first platen and first slurry being selective to the barrier layer. The exposed barrier layer is then polished by using a second platen and second slurry. The first slurry has a copper to barrier polishing selectivity of greater than 30.

Abstract: A method for improving edge peeling defect is disclosed in this invention. According to this invention, a wafer can be kept from the edge peeling defect of the prior art by introducing a step for removing the weakly adhesive films and the metal structures at the wafer edge after forming a metal interconnect layer on the wafer. Thus, this invention can raise the yield of semiconductor manufacturing, and reduce the pollution chance of the chamber of the semiconductor manufacture.

Abstract: This invention relates to a method of forming a dual damascene via, in particular to a method of forming a dual damascene via by using a metal hard mask layer. The present invention uses a metal layer to be a hard mask layer to make the surface of the isolation layer become a level and smooth surface and not become a rounding convex and to prevent the via being connected with others vias to cause the leakage defects after forming the shape of the via.

Abstract: A wafer carrier assembly for a chemical mechanical polishing apparatus and a polishing method using the same are provided. The present wafer carrier assembly comprises a first plate, a second plate and a flexible membrane. The first plate has a plurality of protrusions formed on a bottom surface thereof and the second plate has a plurality of apertures passing through. Each of the protrusions is matched with one of the apertures to enable the first plate and the second plate to detachably combine together. The flexible membrane is positioned under the second plate and contacts it. A surface of the flexible membrane opposite to the surface of the flexible membrane contacting the second plate provides a wafer-receiving surface.

Abstract: In accordance with the present invention, a system for planarizing a substrate in fabricating semiconductor devices is provided. The system comprises at least two different types of polishing module which are arranged in an arbitrary sequence beginning with a first polishing module and ending with a last polishing module, means for transferring the substrate between the polishing modules, a load station, and an unload station. The load station is for loading the transferring means with the substrate prior to starting polishing at the first polishing module, and the unload station is for unloading the substrate from the transferring means after ending polishing at the last polishing module. A method for planarizing a substrate in fabricating semiconductor devices by using a polishing system is also provided.