Patents by Inventor Chia-Lin Liu

Chia-Lin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210057231
    Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 25, 2021
    Inventors: Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen, Ru-Gun Liu, Shau-Lin Shue, Tsai-Sheng Gau, Yung-Hsu Wu
  • Patent number: 10930551
    Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hsiang-Wei Liu, Tai-I Yang, Chia-Tien Wu, Hai-Ching Chen, Shau-Lin Shue
  • Publication number: 20210043503
    Abstract: An electrical connection structure includes a substrate, a mating layer on the substrate, a connecting pad on the mating layer, an insulating layer on the mating layer and covering the connecting pad, a connecting line on the insulating layer, and a covering layer on the insulating layer and covering the connecting line. The connecting line extends through the insulating layer to electrically couple to the connecting pad. Both the connecting pad and the connecting line are made of metal or alloy. The mating layer includes yttrium oxide films and silicon oxide films alternating with each other.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Inventors: CHIN-YUEH LIAO, CHIA-LIN LIU, YAN-TANG DAI, HUNG-CHE LU
  • Publication number: 20210013098
    Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20200411374
    Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hsiang-Wei Liu, Tai-I Yang, Chia-Tien Wu, Hai-Ching Chen, Shau-Lin Shue
  • Publication number: 20200410152
    Abstract: A method includes: receiving a library associated with a cell; determining a plurality of candidate hold times for the cell; acquiring a plurality of candidate setup times corresponding to the plurality of candidate hold times, wherein a data delay associated with each of the candidate setup time fulfills a data delay constraint for the cell; adding the plurality of candidate setup times to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows; and selecting a target time window having a minimal time span among the candidate time windows. At least one of the receiving, determining, acquiring, adding and selecting steps is conducted by at least one processor.
    Type: Application
    Filed: September 15, 2020
    Publication date: December 31, 2020
    Inventors: CHIA HAO TU, HSUEH-CHIH CHOU, SANG HOO DHONG, JERRY CHANG JUI KAO, CHI-LIN LIU, CHENG-CHUNG LIN, SHANG-CHIH HSIEH
  • Patent number: 10867957
    Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Ming-Kai Liu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang, Chia-Chun Miao, Hung-Jen Lin
  • Patent number: 10854133
    Abstract: A micro LED display panel includes a first metal layer, a micro LED layer on the first metal layer, and a transparent conductive layer on a side of the micro LED layer opposite from the first metal layer. The micro LED layer includes a plurality of micro LEDs spaced apart from each other. The first metal layer includes a plurality of first metal units spaced apart from each other. The plurality of first metal units serve as anodes or cathodes of the plurality of micro LEDs. The transparent conductive layer includes a plurality of transparent conductive units spaced apart from each other. The plurality of transparent conductive units serve as anodes or cathodes of the plurality of micro LEDs and are multiplexed as touch electrodes. The micro LED display panel of the present disclosure has both a display function and a touch function.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: December 1, 2020
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chia-Lin Liu, Yu-Fu Weng, Chien-Wen Lin, Tzu-Yu Cheng
  • Patent number: 10854509
    Abstract: A method for making an electrical connection structure includes: providing a substrate; forming a mating layer on the substrate; forming a connecting pad on the mating layer; forming a connecting line on the connecting pad and electrically coupling to the connecting pad; forming a covering layer covering the connecting line; and light irradiating the covering layer. Both the connecting pad and the connecting line are made of a metal or an alloy. The mating layer includes alternating yttrium oxide films and silicon oxide films.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: December 1, 2020
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chin-Yueh Liao, Chia-Lin Liu, Yan-Tang Dai, Hung-Che Lu
  • Publication number: 20200348241
    Abstract: A single-shot metrology for direct inspection of an entirety of the interior of an EUV vessel is provided. An EUV vessel including an inspection tool integrated with the EUV vessel is provided. During an inspection process, the inspection tool is moved into a primary focus region of the EUV vessel. While the inspection tool is disposed at the primary focus region and while providing a substantially uniform and constant light level to an interior of the EUV vessel by way of an illuminator, a panoramic image of an interior of the EUV vessel is captured by way of a single-shot of the inspection tool. Thereafter, a level of tin contamination on a plurality of components of the EUV vessel is quantified based on the panoramic image of the interior of the EUV vessel. The quantified level of contamination is compared to a KPI, and an OCAP may be implemented.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Chun-Lin Louis CHANG, Shang-Chieh CHIEN, Shang-Ying WU, Li-Kai CHENG, Tzung-Chi FU, Bo-Tsun LIU, Li-Jui CHEN, Po-Chung CHENG, Anthony YEN, Chia-Chen CHEN
  • Patent number: 10824784
    Abstract: A method is provided. A library associated with a cell is received. A minimum setup time of the cell is acquired in response to an ideal hold time according to the library and a reference clock. A maximum hold time of the cell is acquired in response to the minimum setup time according to the library and the reference clock. A plurality of candidate hold times are determined. A plurality of candidate setup times are acquired corresponding to the plurality of candidate hold times according to the library and the reference clock. The plurality of candidate setup times are added to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows. A target time window is selected that has a minimal time span among the candidate time windows.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: November 3, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia Hao Tu, Hsueh-Chih Chou, Sang Hoo Dhong, Jerry Chang Jui Kao, Chi-Lin Liu, Cheng-Chung Lin, Shang-Chih Hsieh
  • Patent number: 10818509
    Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen, Ru-Gun Liu, Shau-Lin Shue, Tsai-Sheng Gau, Yung-Hsu Wu
  • Publication number: 20200325304
    Abstract: A thermosetting resin composition and a printed circuit board including the same are provided. The composition adopts a thermosetting polyphenylene ether resin whose terminal functional group is a styrene and an acrylic. The thermosetting polyphenylene ether resin has an appropriate hydroxyl value to be easily cured, and the ratio of two different functional groups is between 0.5 and 1.5, for adjusting heat resistance, fluidity, and filling property. A particle diameter of 1 ?m to 40 ?m is added to control a dielectric constant, and after curing characteristics of high dielectric constant, low dielectric loss, high Tg, high rigidity, high flame resistance and low moisture absorption rate can be achieved.
    Type: Application
    Filed: November 11, 2019
    Publication date: October 15, 2020
    Inventors: TE-CHAO LIAO, HAO-SHENG CHEN, HUNG-YI CHANG, CHIA-LIN LIU, CHIH-KAI CHANG
  • Publication number: 20200313029
    Abstract: Structures and techniques introduced here enable the design and fabrication of photodetectors (PDs) and/or other electronic circuits using typical semiconductor device manufacturing technologies meanwhile reducing the adverse impacts on PDs' performance. Examples of the various structures and techniques introduced here include, but not limited to, a pre-PD homogeneous wafer bonding technique, a pre-PD heterogeneous wafer bonding technique, a post-PD wafer bonding technique, their combinations, and a number of mirror equipped PD structures. With the introduced structures and techniques, it is possible to implement PDs using typical direct growth material epitaxy technology while reducing the adverse impact of the defect layer at the material interface caused by lattice mismatch.
    Type: Application
    Filed: April 14, 2020
    Publication date: October 1, 2020
    Inventors: Chien-Yu Chen, Szu-Lin Cheng, Chieh-Ting Lin, Yu-Hsuan Liu, Ming-Jay Yang, Shu-Lu Chen, Tsung-Ting Wu, Chia-Peng Lin, Yun-Chung Na, Hui-Wen Chen, Han-Din Liu
  • Patent number: 10790189
    Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 10781297
    Abstract: A thermosetting resin composition contains a primary resin formed from mixing a styrene-type polyphenylene ether resin thermally modified with styrene with an acrylic-type polyphenylene ether resin thermally modified with acrylic at a weight ratio ranging between 0.5 and 1.5, consequently having excellent heat resistance, flowability, and filling ability; and when cured, having a dielectric constant smaller than 3.0 and a dielectric dissipation factor smaller less than 0.0020 at the frequency of 1 GHz as well as a glass transition temperature higher than 210° C.; in application, the composition is suitable to impregnate reinforcement to form prepregs with excellent curability.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: September 22, 2020
    Assignee: Nan Ya Plastics Corporation
    Inventors: Te-Chao Liao, Ying-Te Huang, Hao-Sheng Chen, Hung-Yi Chang, Chia-Lin Liu
  • Publication number: 20200285797
    Abstract: A layout method comprises selecting a first and a second layout devices in a layout of an integrated circuit. The second layout device abuts the first layout device at a boundary therebetween. The layout method also comprises disposing a first and a second conductive paths across the boundary, and respectively disposing a first and a second cut layers on the first and second conductive paths nearby the boundary. The layout method also comprises disconnecting the first layout device from the second layout device by cutting the first conductive path into two conductive portions according to a first position of the first cut layer and cutting the second conductive path into two conductive portions a second position of the second cut layer. The layout method also comprises moving the first cut layer to align with the second cut layer.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: CHEOK-KEI LEI, YU-CHI LI, CHIA-WEI TSENG, ZHE-WEI JIANG, CHI-LIN LIU, JERRY CHANG-JUI KAO, JUNG-CHAN YANG, CHI-YU LU, HUI-ZHONG ZHUANG
  • Publication number: 20200286738
    Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a patterning process; and forming a second plurality of trenches in the first layer by another patterning process, resulting in combined trench patterns in the first layer. A first trench of the second plurality connects two trenches of the first plurality. The method further includes forming dielectric spacer features on sidewalls of the combined trench patterns. A space between two opposing sidewalls of the first trench is completely filled by the dielectric spacer features and another space between two opposing sidewalls of one of the two trenches is partially filled by the dielectric spacer features.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 10, 2020
    Inventors: RU-GUN LIU, CHENG-HSIUNG TSAI, CHUNG-JU LEE, CHIH-MING LAI, CHIA-YING LEE, JYU-HORNG SHIEH, KEN-HSIEN HSIEH, MING-FENG SHIEH, SHAU-LIN SHUE, SHIH-MING CHANG, TIEN-I BAO, TSAI-SHENG GAU
  • Patent number: 10748940
    Abstract: A TFT substrate for a touch display panel of reduced thickness defines a display area and a surrounding non-display area. The TFT substrate includes a first conductive layer on the substrate and a second conductive layer on the first conductive layer. In the display area, the first conductive layer includes data lines and the second conductive layer includes common electrodes. Each common electrode extends as a strip along a first direction. Each data line extends along a second direction. The first direction intersects the second direction. Each data line crosses the common electrodes. Each data line functions as a touch driving electrode and each common electrode functions as a touch sensing electrode.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: August 18, 2020
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chia-Lin Liu, Yu-Fu Weng, Chien-Wen Lin, Tzu-Yu Cheng
  • Publication number: 20200243664
    Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided, in which the method includes the steps of forming a gate structure on a substrate, forming a spacer on a sidewall of the gate structure, forming two recesses adjacent to two sides of the spacer, performing a cleaning process to trim the spacer for forming a void between the spacer and the substrate, and forming two portions of an epitaxial layer in the two recesses. The semiconductor device preferably includes a cap layer on the two portions of the epitaxial layer as the cap layer includes a planar top surface and an inclined sidewall.
    Type: Application
    Filed: March 6, 2019
    Publication date: July 30, 2020
    Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu