Abstract: A substrate structure is provided, in which an insulating protection layer is formed on a substrate body having a plurality of electrical contact pads, and the insulating protection layer has a plurality of openings corresponding to the plurality of exposed electrical contact pads, and the insulating protection layer is formed with a hollow portion surrounding a partial edge of at least one of the electrical contact pads at at least one of the openings, so as to reduce the barrier of the insulating protection layer.

Abstract: A method includes: receiving a design layout comprising a feature extending in a peripheral region and a central region of the design layout; determining compensation values associated with a pellicle assembly and the peripheral region according to an exposure distribution in an exposure field of a workpiece; and adjusting the design layout according to the compensation values. The modifying of the shape of the feature according to the compensation values includes: partitioning the peripheral region into compensation zones; and adjusting line widths in the compensation zones of the feature according to the compensation values associated with the respective compensation zones.

Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.

Abstract: An electrostatic discharge (ESD) circuit includes a first ESD detection circuit, a first discharging circuit and a first ESD assist circuit. The first ESD detection circuit is coupled between a first node having a first voltage and a second node having a second voltage. The first discharging circuit includes a first transistor. The first transistor has a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to the first ESD detection circuit by a third node. The first drain is coupled to the first node. The first source and the first body terminal are coupled together at the second node. The first ESD assist circuit is coupled between the second and third node, and configured to clamp a third voltage of the third node at the second voltage during an ESD event at the first or second node.

Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.

Abstract: In a file sharing system, a key manager unit realizes a correspondence between the first user identifier and the first public key in response to a registration request of the first user, generates a first key material for encrypting the first file into a first encrypted file, and generates a first credential according to the first user identifier, the first file identifier, the first public key and the first key material after receiving an access-right claim request to the first file from the first user. A file storage unit stores the first encrypted file and the first credential. The first user uses the first user identifier, the first file identifier and the first private key to retrieve the first key material out of the first credential, and uses the first key material to decrypt the first encrypted file into the first file.

Abstract: An optical member driving mechanism is provided. The optical member driving mechanism is configured to hold an optical member and drive the optical member to move. The optical member driving mechanism includes a first movable portion, a fixed portion, and a driving assembly. The first movable portion is movable relative to the fixed portion. The driving assembly is configured to drive the first movable portion to move relative to the fixed portion.

Abstract: A wafer inspection system is provided. The wafer inspection system includes a memory unit configured to store an image of a device under test (DUT) on a wafer, an image-uploading unit configured to upload the image to a processing unit, and a processing unit. The processing unit is configured to identify a plurality of candidate regions on the image; generate a confidence score for each of the plurality of candidate regions, wherein the confidence score indicates a probability of a candidate region including a probe mark; select a first candidate region having the highest confidence score as a selected region; determine whether a second candidate region in the plurality of candidate regions includes the same probe mark as the first candidate region; and eliminate the second candidate region if the second candidate region includes the same probe mark as the first candidate region.

Abstract: A wafer inspection method is provided. The wafer inspection method includes identifying a plurality of candidate regions on an image of a DUT on a wafer; generating a confidence score for each of the plurality of candidate regions, wherein the confidence score indicates a probability of a candidate region including a probe mark; selecting a first candidate region having the highest confidence score as a selected region; determining whether a second candidate region in the plurality of candidate regions includes the same probe mark as the first candidate region; and eliminating the second candidate region if the second candidate region includes the same probe mark as the first candidate region.

Abstract: A wafer test system includes a probe apparatus, a data server, an automation subsystem, and a probe mark assessment subsystem. The probe apparatus includes a probe card, a tester, and a camera. The probe card includes probe pins for contacting test pads in the wafer, and the camera captures an image of the test pads. The automation subsystem obtains an image specification from the probe apparatus and triggers an automated assessment of a probe mark in the image of the test pads. The probe mark assessment subsystem performs the automated assessment of the probe mark in the image of the test pads. The probe mark assessment subsystem performs an image-processing operation to obtain a probe mark assessment result, and the automation subsystem stops the probe apparatus if the probe mark assessment result indicates a probe test failure.

Abstract: The present disclosure provides a wafer test system and methods thereof. The test system includes a probe apparatus, a data server, an automation subsystem, and a probe mark assessment subsystem. The probe apparatus includes a probe card, a tester, and a camera. The probe card includes probe pins for contacting test pads in the wafer, and the camera captures an image of the test pads. The automation subsystem obtains an image specification from the probe apparatus and triggers an automated assessment of a probe mark in the image of the test pads. The probe mark assessment subsystem performs the automated assessment of the probe mark in the image of the test pads. The probe mark assessment subsystem performs an image-processing operation to obtain a probe mark assessment result, and the automation subsystem stops the probe apparatus if the probe mark assessment result indicates a probe test failure.

Abstract: A chip includes pads having first connecting surfaces, and conductive structures located on the first connecting surfaces. The conductive structures are disposed on the first connecting surfaces. Each of the conductive structures includes first metal layer, second metal layer, and third metal layer. The first metal layer connects one of the pads, and the second metal layer is disposed between the first metal layer and the third metal layer. On every pad, the first metal layer, the second metal layer, and the third metal layer are stacked along first direction on the first connecting surface of the pad, and the first direction is parallel to normal direction of the first connecting surface, and the first metal layer is made of material comprising gold, and the second metal layer is made of material comprising nickel. A wafer is also provided.

Abstract: Provided is an adsorption material including a plurality of porous silicate particles having a glass-phase structure and including silicon oxide, aluminum oxide, barium oxide, strontium oxide and boron oxide. An average pore size of the plurality of porous silicate particles is in a range of from 3 nm to 50 nm, and a zeta potential of the plurality of porous silicate particles is negative at a pH value of from 1 to 5. A method of fabricating the adsorption material is further provided.

Abstract: A case assembly of an electronic device includes a first outer case and an inner case. The first outer case includes a holding groove and a holding plate for forming the holding groove. The holding plate includes a touching surface and a pressing surface that are opposite to each other, and the touching surface forms a part of the holding groove. The inner case is disposed on one side of the first outer case. The inner case includes a surface and at least one supporting component protruding from the surface. The at least one supporting component abuts against the pressing surface, and the inner case and the at least one supporting component are integrated together.

Abstract: A case assembly of an electronic device includes a first outer case and an inner case. The first outer case includes a holding groove and a holding plate for forming the holding groove. The holding plate includes a touching surface and a pressing surface that are opposite to each other, and the touching surface forms a part of the holding groove. The inner case is disposed on one side of the first outer case. The inner case includes a surface and at least one supporting component protruding from the surface. The at least one supporting component abuts against the pressing surface, and the inner case and the at least one supporting component are integrated together.

Abstract: Provided are methods for recycling liquid crystal comprising: receiving at least one liquid crystal mixture; and forming a reformulated liquid crystal mixture using at least one portion of the at least one liquid crystal mixture. Also provided are reformulated liquid crystal mixtures comprising at least one recycled liquid crystal mixture and liquid crystals displays devices having one or more reformulated liquid crystal mixtures.

Abstract: Provided are methods for recycling liquid crystal comprising: receiving at least one liquid crystal mixture; and forming a reformulated liquid crystal mixture using at least one portion of the at least one liquid crystal mixture. Also provided are reformulated liquid crystal mixtures comprising at least one recycled liquid crystal mixture and liquid crystals displays devices having one or more reformulated liquid crystal mixtures.

Abstract: An image output/input system includes a phase comparator, an image synchronous signal generator, a sensor timing generator, a sensor, an image/color processing unit, and a video encoder. The phase comparator receives a digital signal and a vertical synchronous signal and compares their period and phase to generate a clock correction signal. The image synchronous signal generator receives the clock correction signal and adjusts a subsequent period of the vertical synchronous signal according to the clock correction signal. The sensor timing generator receives the vertical synchronous signal and generates the sensor control timing, and the sensor receives the sensor control timing and generates raw image data. The image/color processing unit receives the raw image data and deals with the image and color process of the raw image data to generate target image data. The video encoder receives the vertical synchronous signal and the target image data and encodes them to generate analog encoded image data.