Patents by Inventor Chia-Lin Tsai

Chia-Lin Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250126732
    Abstract: A bracket for a computing device includes a bracket backwall having a height H1, a first bracket sidewall coupled to a first corner of the bracket backwall, and a second bracket sidewall coupled to a second corner of the bracket backwall. The first bracket sidewall has a height H2,The second bracket sidewall is coupled to a second corner of the bracket backwall. The second corner is opposite the first corner along a diagonal of the bracket backwall. The second bracket sidewall has a height H2. The bracket further includes a first PCIe securing tab extending from the first bracket sidewall towards the second bracket sidewall, and a second PCIe securing tab extending from the second bracket sidewall towards the first bracket sidewall. The height H1 is approximately equal to a sum of the height H2 and the height H3.
    Type: Application
    Filed: December 26, 2023
    Publication date: April 17, 2025
    Inventors: Yaw-Tzorng TSORNG, Jen-Jia LIOU, Wei-Jie CHEN, Chia-Lin TSAI
  • Publication number: 20250120037
    Abstract: A server system is disclosed. The server system includes a riser bracket having a slot and an internal space, the internal space being an operation space for allowing a physical user action; a Peripheral Component Interconnect Express (PCIE) card inserted in the slot of the riser bracket, the PCIE card having a power connector, the power connector being configured to receive a power cable, the internal space being adjacent to the power connector; and a hinge mechanically coupled to the riser bracket near the power connector, the hinge being pivotable between a first position and a second position, the hinge covering the internal space in the first position, the hinge uncovering the internal space in the second position.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 10, 2025
    Inventors: Yaw-Tzorng TSORNG, Jen-Jia LIOU, Chia-Lin TSAI, Fu-Jun YU
  • Patent number: 12211200
    Abstract: A wafer inspection method is provided. The wafer inspection method includes identifying a plurality of candidate regions on an image of a DUT on a wafer; generating a confidence score for each of the plurality of candidate regions, wherein the confidence score indicates a probability of a candidate region including a probe mark; selecting a first candidate region having the highest confidence score as a selected region; determining whether a second candidate region in the plurality of candidate regions includes the same probe mark as the first candidate region; and eliminating the second candidate region if the second candidate region includes the same probe mark as the first candidate region.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: January 28, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chia-Lin Tsai, Hung-Ru Li, Wun-Ye Ku
  • Publication number: 20240404040
    Abstract: A test system is provided, including an assessment subsystem, a neural network subsystem and a process control processor. The assessment subsystem receives a test image of a tested wafer from a probe apparatus. The process control processor controls, in response to the probe apparatus obtaining the test image, the assessment subsystem to perform an assessment operation to transmit the test image to the neural network subsystem in an automation mode. The neural network subsystem identifies an image specification of probe marks in the test image and generates an analyzed data of the test image to the assessment subsystem. The assessment subsystem further generates a first probe mark inspection result based on the analyzed data to the process control processor for generating a test result.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 5, 2024
    Inventor: Chia-Lin TSAI
  • Patent number: 12148144
    Abstract: A wafer inspection system is provided. The wafer inspection system includes a memory unit configured to store an image of a device under test (DUT) on a wafer, an image-uploading unit configured to upload the image to a processing unit, and a processing unit. The processing unit is configured to identify a plurality of candidate regions on the image; generate a confidence score for each of the plurality of candidate regions, wherein the confidence score indicates a probability of a candidate region including a probe mark; select a first candidate region having the highest confidence score as a selected region; determine whether a second candidate region in the plurality of candidate regions includes the same probe mark as the first candidate region; and eliminate the second candidate region if the second candidate region includes the same probe mark as the first candidate region.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: November 19, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chia-Lin Tsai, Hung-Ru Li, Wun-Ye Ku
  • Publication number: 20230334648
    Abstract: A wafer inspection method is provided. The wafer inspection method includes identifying a plurality of candidate regions on an image of a DUT on a wafer; generating a confidence score for each of the plurality of candidate regions, wherein the confidence score indicates a probability of a candidate region including a probe mark; selecting a first candidate region having the highest confidence score as a selected region; determining whether a second candidate region in the plurality of candidate regions includes the same probe mark as the first candidate region; and eliminating the second candidate region if the second candidate region includes the same probe mark as the first candidate region.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 19, 2023
    Inventors: CHIA-LIN TSAI, HUNG-RU LI, WUN-YE KU
  • Publication number: 20230334647
    Abstract: A wafer inspection system is provided. The wafer inspection system includes a memory unit configured to store an image of a device under test (DUT) on a wafer, an image-uploading unit configured to upload the image to a processing unit, and a processing unit. The processing unit is configured to identify a plurality of candidate regions on the image; generate a confidence score for each of the plurality of candidate regions, wherein the confidence score indicates a probability of a candidate region including a probe mark; select a first candidate region having the highest confidence score as a selected region; determine whether a second candidate region in the plurality of candidate regions includes the same probe mark as the first candidate region; and eliminate the second candidate region if the second candidate region includes the same probe mark as the first candidate region.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 19, 2023
    Inventors: CHIA-LIN TSAI, HUNG-RU LI, WUN-YE KU
  • Patent number: 11486899
    Abstract: A wafer test system includes a probe apparatus, a data server, an automation subsystem, and a probe mark assessment subsystem. The probe apparatus includes a probe card, a tester, and a camera. The probe card includes probe pins for contacting test pads in the wafer, and the camera captures an image of the test pads. The automation subsystem obtains an image specification from the probe apparatus and triggers an automated assessment of a probe mark in the image of the test pads. The probe mark assessment subsystem performs the automated assessment of the probe mark in the image of the test pads. The probe mark assessment subsystem performs an image-processing operation to obtain a probe mark assessment result, and the automation subsystem stops the probe apparatus if the probe mark assessment result indicates a probe test failure.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: November 1, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chia-Lin Tsai, Wun-Ye Ku, Tien-Yu Chen, Chia-Yi Lin
  • Publication number: 20210239736
    Abstract: The present disclosure provides a wafer test system and methods thereof. The test system includes a probe apparatus, a data server, an automation subsystem, and a probe mark assessment subsystem. The probe apparatus includes a probe card, a tester, and a camera. The probe card includes probe pins for contacting test pads in the wafer, and the camera captures an image of the test pads. The automation subsystem obtains an image specification from the probe apparatus and triggers an automated assessment of a probe mark in the image of the test pads. The probe mark assessment subsystem performs the automated assessment of the probe mark in the image of the test pads. The probe mark assessment subsystem performs an image-processing operation to obtain a probe mark assessment result, and the automation subsystem stops the probe apparatus if the probe mark assessment result indicates a probe test failure.
    Type: Application
    Filed: January 31, 2020
    Publication date: August 5, 2021
    Inventors: CHIA-LIN TSAI, WUN-YE KU, TIEN-YU CHEN, CHIA-YI LIN
  • Patent number: 11063011
    Abstract: A chip includes pads having first connecting surfaces, and conductive structures located on the first connecting surfaces. The conductive structures are disposed on the first connecting surfaces. Each of the conductive structures includes first metal layer, second metal layer, and third metal layer. The first metal layer connects one of the pads, and the second metal layer is disposed between the first metal layer and the third metal layer. On every pad, the first metal layer, the second metal layer, and the third metal layer are stacked along first direction on the first connecting surface of the pad, and the first direction is parallel to normal direction of the first connecting surface, and the first metal layer is made of material comprising gold, and the second metal layer is made of material comprising nickel. A wafer is also provided.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: July 13, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chia-Lin Tsai, Mao-Ying Wang
  • Publication number: 20160375422
    Abstract: Provided is an adsorption material including a plurality of porous silicate particles having a glass-phase structure and including silicon oxide, aluminum oxide, barium oxide, strontium oxide and boron oxide. An average pore size of the plurality of porous silicate particles is in a range of from 3 nm to 50 nm, and a zeta potential of the plurality of porous silicate particles is negative at a pH value of from 1 to 5. A method of fabricating the adsorption material is further provided.
    Type: Application
    Filed: December 11, 2015
    Publication date: December 29, 2016
    Inventors: Chia-Lin Tsai, Cheng-Kuo Tsai, Huan-Yi Hung, Pang-Hung Liu, Hsien-Hui Tai
  • Patent number: 9360886
    Abstract: A case assembly of an electronic device includes a first outer case and an inner case. The first outer case includes a holding groove and a holding plate for forming the holding groove. The holding plate includes a touching surface and a pressing surface that are opposite to each other, and the touching surface forms a part of the holding groove. The inner case is disposed on one side of the first outer case. The inner case includes a surface and at least one supporting component protruding from the surface. The at least one supporting component abuts against the pressing surface, and the inner case and the at least one supporting component are integrated together.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 7, 2016
    Assignee: TPV-INVENTA TECHNOLOGY CO., LTD.
    Inventors: Shao-Tzu Hsu, Chia-Lin Tsai, Chun-An Wu
  • Publication number: 20160044810
    Abstract: A case assembly of an electronic device includes a first outer case and an inner case. The first outer case includes a holding groove and a holding plate for forming the holding groove. The holding plate includes a touching surface and a pressing surface that are opposite to each other, and the touching surface forms a part of the holding groove. The inner case is disposed on one side of the first outer case. The inner case includes a surface and at least one supporting component protruding from the surface. The at least one supporting component abuts against the pressing surface, and the inner case and the at least one supporting component are integrated together.
    Type: Application
    Filed: March 27, 2015
    Publication date: February 11, 2016
    Inventors: Shao-Tzu Hsu, Chia-Lin Tsai, Chun-An Wu
  • Patent number: 8968595
    Abstract: Provided are methods for recycling liquid crystal comprising: receiving at least one liquid crystal mixture; and forming a reformulated liquid crystal mixture using at least one portion of the at least one liquid crystal mixture. Also provided are reformulated liquid crystal mixtures comprising at least one recycled liquid crystal mixture and liquid crystals displays devices having one or more reformulated liquid crystal mixtures.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: March 3, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Wei Lu, Huan-Yi Hung, Tsung-Chou Hsu, Chia-Lin Tsai, Yao-Ting Huang, Meng-Yuh Chen
  • Publication number: 20130056679
    Abstract: Provided are methods for recycling liquid crystal comprising: receiving at least one liquid crystal mixture; and forming a reformulated liquid crystal mixture using at least one portion of the at least one liquid crystal mixture. Also provided are reformulated liquid crystal mixtures comprising at least one recycled liquid crystal mixture and liquid crystals displays devices having one or more reformulated liquid crystal mixtures.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 7, 2013
    Applicant: Industrial Technology Research Institute
    Inventors: Chien-Wei LU, Huan-Yi Hung, Tsung-Chou Hsu, Chia-Lin Tsai, Yao-Ting Huang, Meng-Yuh Chen
  • Patent number: 7671897
    Abstract: An image output/input system includes a phase comparator, an image synchronous signal generator, a sensor timing generator, a sensor, an image/color processing unit, and a video encoder. The phase comparator receives a digital signal and a vertical synchronous signal and compares their period and phase to generate a clock correction signal. The image synchronous signal generator receives the clock correction signal and adjusts a subsequent period of the vertical synchronous signal according to the clock correction signal. The sensor timing generator receives the vertical synchronous signal and generates the sensor control timing, and the sensor receives the sensor control timing and generates raw image data. The image/color processing unit receives the raw image data and deals with the image and color process of the raw image data to generate target image data. The video encoder receives the vertical synchronous signal and the target image data and encodes them to generate analog encoded image data.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: March 2, 2010
    Assignee: Sonix Technology Co., Ltd.
    Inventor: Chia-Lin Tsai
  • Publication number: 20080002034
    Abstract: An image output system includes a phase comparator, an image synchronous signal generator, and a video encoder. The phase comparator receives a digital signal and a vertical synchronous signal and compares their period and phase to generate a clock correction signal, where the digital signal is converted from an analog signal through a voltage comparator (or the analog-to-digital conversion). The image synchronous signal generator receives the clock correction signal, generates the vertical synchronous signal, and adjusts a subsequent period of the vertical synchronous signal according to the clock correction signal. The video encoder receives the vertical synchronous signal and target image data and encodes them to output an analog encoded image data.
    Type: Application
    Filed: June 29, 2006
    Publication date: January 3, 2008
    Inventor: Chia-Lin Tsai
  • Patent number: 7251130
    Abstract: A computer system with vertically offset hard disk drives has a space in one side for containing the two vertically offset hard disk drives held by a mobile rack in a vertically offset manner. The mobile rack fixes the two hard disk drives with two vertically offset screw sets. A holding frame in the space of the computer system has two vertically offset connectors that allow the two hard disk drives to be connected at the same time when the mobile rack is completely inserted into the holding frame.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: July 31, 2007
    Assignee: Micro-Star Int'l Co., Ltd.
    Inventor: Chia-Lin Tsai
  • Patent number: D599382
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: September 1, 2009
    Inventor: Chia-Lin Tsai
  • Patent number: D599383
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: September 1, 2009
    Inventor: Chia-Lin Tsai