Patents by Inventor Chia Lin

Chia Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240112957
    Abstract: A fabrication method is disclosed that includes: forming a first metal layer over first and second semiconductor structures; forming a first patterned photolithographic layer with an opening that exposes a portion of the first metal layer over the first semiconductor structure but not to a boundary between semiconductor structures; removing the exposed portion of the first metal layer; forming a second metal layer over the first and second semiconductor structures; forming a second patterned photolithographic layer with an opening that exposes a portion of the second metal layer over the second semiconductor structure but not to the boundary; removing the exposed portion of the first and second metal layers; wherein a barrier structure is generated between the first and second semiconductor structures that includes remaining portions of the first metal layer and a portion of the second metal layer overlying the remaining portions of the first metal layer.
    Type: Application
    Filed: January 12, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Xuan Wang, Cheng-Chun Tseng, Yi-Chun Chen, Yu-Hsien Lin, Ryan Chia-Jen Chen
  • Publication number: 20240113071
    Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 4, 2024
    Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
  • Publication number: 20240112912
    Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (Al) or formula (A2): Zr12O8(OH)14(RCO2)18??Formula (A1); or Hf6O4(OH)6(RCO2)10??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.
    Type: Application
    Filed: July 28, 2023
    Publication date: April 4, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Jui-Hsiung LIU, Yu-Fang TSENG, Pin-Chia LIAO, Burn Jeng LIN, Tsai-Sheng GAU, Po-Hsiung CHEN, Po-Wen CHIU
  • Publication number: 20240112791
    Abstract: A system, apparatus, and method align tokens representing the state of a person under care with at least one stakeholder represented by further tokens. The system identifies incentives in multi-party interactions where such incentives are represented by specification value pairs and through the use of game theory, machine leaning, pattern identification and recognition and/or digital twins in any arrangement, misalignment of such specification value pairs may be identified and responded to in manner that can avoid and/or mitigate the impact of such misalignments on the interactions of those parties, including in pursuit of the reduction of fraud or other undesirable behaviors within at least one system.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 4, 2024
    Applicant: LogicMark, Inc.
    Inventors: Chia-Lin SIMMONS, Rafael SAAVEDRA, Peter WILLIAMS
  • Publication number: 20240113695
    Abstract: A modulation device including a plurality of electronic elements, at least one first signal line and a first driving circuit is provided. The at least one first signal line is respectively electrically connected to at least one of the electronic elements. The first driving circuit is electrically connected to the at least one first signal line. The first driving circuit provides a first signal to at least one of the at least one first signal line. The first signal includes a first pulse. The first pulse includes a first section and a second section closely adjacent to the first section.
    Type: Application
    Filed: August 30, 2023
    Publication date: April 4, 2024
    Applicant: Innolux Corporation
    Inventors: Yi-Hung Lin, Kung-Chen Kuo, Yu-Chia Huang, Nai-Fang Hsu
  • Publication number: 20240113164
    Abstract: A process for converting a portion of a dielectric fill material into a hard mask includes a nitrogen treatment or nitrogen plasma to convert a portion of the dielectric fill material into a nitrogen-like layer for serving as a hard mask to form an edge area of a device die by an etching process. After forming the edge area, another dielectric fill material is provided in the edge area. In the completed device, a gate cut area can have a gradient of nitrogen concentration at an upper portion of the gate cut dielectric of the gate cut area.
    Type: Application
    Filed: January 9, 2023
    Publication date: April 4, 2024
    Inventors: Heng-Chia Su, Li-Fong Lin, Zhen-Cheng Wu, Chi On Chui
  • Publication number: 20240113099
    Abstract: An IC device includes first and second CMOS structures positioned in n-type doped regions of a substrate, the first CMOS structure including a common gate terminal, first NMOS body and source contacts, and first PMOS body and source contacts, the second CMOS structure including a common drain terminal, second NMOS body and source contacts, and second PMOS body and source contacts. The IC device includes a first electrical connection from the common drain terminal to the common gate terminal, a clamp device including a diode, a second electrical connection from a cathode of the diode to the first PMOS body and source contacts, and a third electrical connection from an anode of the of the diode to the first NMOS body and source contacts, and entireties of each of the second and third electrical connections are positioned between the substrate and a third metal layer of the IC device.
    Type: Application
    Filed: April 28, 2023
    Publication date: April 4, 2024
    Inventors: Chia-Lin HSU, Yu-Ti SU
  • Publication number: 20240113112
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Publication number: 20240112885
    Abstract: Embodiments disclosed herein include a diagnostic substrate. In an embodiment, the diagnostic substrate comprises a substrate and a sensor on the substrate. In an embodiment, the diagnostic substrate further comprises a communication module on the substrate that is communicatively coupled to the sensor. In an embodiment, the communication module comprises an output antenna, a switch coupled to the output antenna, and a signal source coupled to the switch.
    Type: Application
    Filed: July 10, 2023
    Publication date: April 4, 2024
    Inventor: Chuang-Chia Lin
  • Publication number: 20240113414
    Abstract: Disclosed is an electronic device including a device body and an antenna module. The antenna module includes a conductive element and at least one antenna element. The conductive element includes a main body portion and at least one assembly portion connected with each other. The at least one assembly portion is assembled on the device body. The at least one antenna element is disposed on the device body and coupled with the conductive element to excite a first resonance mode. The at least one assembly portion overlaps the at least one antenna element in the length direction of the main body portion.
    Type: Application
    Filed: September 24, 2023
    Publication date: April 4, 2024
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Chih-Heng Lin, Li-Chun Lee, Shih-Chia Liu, Jui-Hung Lai, Hung-Yu Yeh
  • Publication number: 20240114727
    Abstract: Embodiments described herein relate to a sub-pixel. The sub-pixel includes an anode, overhang structures, separation structures, an organic light emitting diode (OLED) material, and a cathode. The anode is defined by adjacent first pixel isolation structures (PIS) and adjacent second PIS. The overhang structures are disposed on the first PIS. The overhang structures include a second structure disposed over the first structure and an intermediate structure disposed between the second structure and the first structure. A bottom surface of the second structure extends laterally past an upper surface of the first structure. The first structure is disposed over the first PIS. Separation structures are disposed over the second PIS. The OLED material is disposed over the anode and an upper surface of the separation structures. The cathode disposed over the OLED material and an upper surface of the separation structures.
    Type: Application
    Filed: December 5, 2023
    Publication date: April 4, 2024
    Inventors: Jungmin LEE, Chung-chia CHEN, Ji Young CHOUNG, Yu-hsin LIN
  • Publication number: 20240112774
    Abstract: A system, apparatus, and method align tokens representing the state of a person under care with at least one stakeholder represented by further tokens. The system identifies incentives in multi-party interactions where such incentives are represented by specification value pairs and through the use of game theory, machine leaning, pattern identification and recognition and/or digital twins in any arrangement, misalignment of such specification value pairs may be identified and responded to in manner that can avoid and/or mitigate the impact of such misalignments on the interactions of those parties, including in pursuit of the reduction of fraud or other undesirable behaviors within at least one system.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 4, 2024
    Applicant: LogicMark, Inc.
    Inventors: Chia-Lin SIMMONS, Rafael SAAVEDRA, Peter WILLIAMS
  • Publication number: 20240105795
    Abstract: A method for fabricating semiconductor devices is disclosed. The method includes forming a gate trench over a semiconductor channel, the gate trench being surrounded by gate spacers. The method includes sequentially depositing a work function metal, a glue metal, and an electrode metal in the gate trench. The method includes etching respective portions of the electrode metal and the glue metal to form a gate electrode above a metal gate structure. The metal gate structure includes a remaining portion of the work function metal and the gate electrode includes a remaining portion of the electrode metal. The gate electrode has an upper surface extending away from a top surface of the metal gate structure.
    Type: Application
    Filed: February 16, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jun-Ye Liu, Jih-Sheng Yang, Yu-Hsien Lin, Ryan Chia-Jen Chen
  • Publication number: 20240102876
    Abstract: Embodiments disclosed herein include diagnostic substrates and methods of using the diagnostic substrates to extract plasma parameters. In an embodiment, a diagnostic substrate comprises a substrate and an array of resonators across the substrate. In an embodiment, the array of resonators comprises at least a first resonator with a first structure and a second resonator with a second structure. In an embodiment, the first structure is different than the second structure.
    Type: Application
    Filed: December 6, 2023
    Publication date: March 28, 2024
    Inventors: CHUANG-CHIA LIN, DAVID PETERSON, PHILIP ALLAN KRAUS, AMIR BAYATI
  • Publication number: 20240106104
    Abstract: An electronic device includes a device body and an antenna module disposed in the device body and including a conductive structure and a coaxial cable including a core wire, a shielding layer wrapping the core wire, and an outer jacket wrapping the shielding layer. The conductive structure includes a structure body and a slot formed on the structure body and penetrating the structure body in a thickness direction of the structure body. A section of the shielding layer extends from the outer jacket and is connected to the structure body. A physical portion of the structure body and the section of the shielding layer are respectively located on two opposite sides of the slot in a width direction of the slot. A section of the core wire extends from the section of the shielding layer and overlaps the slot and the physical portion in the thickness direction.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 28, 2024
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Hung-Yu Yeh, Shih-Chia Liu, Yen-Hao Yu, Li-Chun Lee, Chih-Heng Lin, Jui-Hung Lai
  • Publication number: 20240107819
    Abstract: Embodiments described herein relate to a sub-pixel. The sub-pixel includes an anode, overhang structures, separation structures, an organic light emitting diode (OLED) material, and a cathode. The anode is defined by adjacent first pixel isolation structures (PIS) and adjacent second PIS. The overhang structures are disposed on the first PIS. The overhang structures include a second structure disposed over the first structure and an intermediate structure disposed between the second structure and the first structure. A bottom surface of the second structure extends laterally past an upper surface of the first structure. The first structure is disposed over the first PIS. Separation structures are disposed over the second PIS. The OLED material is disposed over the anode and an upper surface of the separation structures. The cathode disposed over the OLED material and an upper surface of the separation structures.
    Type: Application
    Filed: December 5, 2023
    Publication date: March 28, 2024
    Inventors: Jungmin LEE, Chung-chia CHEN, Ji Young CHOUNG, Yu-hsin LIN
  • Publication number: 20240101485
    Abstract: A powder composition includes a first powder, a second powder, and a modified functional group. A particle size range of the first powder is between 1 micron and 100 microns. The second powder and the modified functional group are modified on the first powder. A particle size range of the second powder is between 10 nanometers and 1 micron. A manufacturing method of a powder composition is also provided.
    Type: Application
    Filed: November 15, 2022
    Publication date: March 28, 2024
    Applicant: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Hung-Yi Chang, Chia-Lin Liu
  • Patent number: 11939431
    Abstract: The present invention relates to a composition comprising an amino acid-modified polymer, a carboxypolysaccharide, and may further include a metal ion for anti-adhesion and vector application. More specifically, the invention relates to a thermosensitive composition having enhanced mechanical and improved water-erosion resistant properties for efficiently preventing tissue adhesions and can serve as a vector with bio-compatible, bio-degradable/absorbable, and in-vivo sustainable properties.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: March 26, 2024
    Assignee: PROVIEW-MBD BIOTECH CO., LTD.
    Inventors: Yu-Chia Chang, Yunn-Kuen Chang, Wen-Yen Huang, Ging-Ho Hsiue, Hsieh-Chih Tsai, Shuian-Yin Lin, Nai-Sheng Hsu, Tzu-Yu Lin
  • Patent number: 11939432
    Abstract: Synthetic amino acid-modified polymers and methods of making the same and using the same are disclosed. The synthetic amino acid-modified polymers possess distinct thermosensitive, improved water-erosion resistant, and enhanced mechanical properties, and are suitable of reducing or preventing formation of postoperative tissue adhesions. Additionally, the amino acid-modified polymers can also be used as a vector to deliver pharmaceutically active agents.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: March 26, 2024
    Assignee: PROVIEW-MBD BIOTECH CO., LTD.
    Inventors: Yu-Chia Chang, Yunn-Kuen Chang, Wen-Yen Huang, Ging-Ho Hsiue, Hsieh-Chih Tsai, Shuian-Yin Lin, Nai-Sheng Hsu, Tzu-Yu Lin
  • Patent number: 11942532
    Abstract: A method includes fabricating a semiconductor device, wherein the method includes depositing a coating layer on a first region and a second region under a loading condition such that a height of the coating layer in the first region is greater than a height of the coating layer in the second region. The method also includes applying processing gas to the coating layer to remove an upper portion of the coating layer such that a height of the coating layer in the first region is a same as a height of the coating layer in the second region.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chao-Hsuan Chen, Ming-Chia Tai, Yu-Hsien Lin, Shun-Hui Yang, Ryan Chia-Jen Chen