Patents by Inventor Chia Lin

Chia Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942467
    Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Sheng Chen, Yi-Jing Li, Chia-Ming Hsu, Wan-Lin Tsai, Clement Hsingjen Wann
  • Patent number: 11943584
    Abstract: A micro-electro-mechanical system (MEMS) microphone is provided. The MEMS microphone includes a substrate, a diaphragm, a backplate and a first protrusion. The substrate has an opening portion. The diaphragm is disposed on one side of the substrate and extends across the opening portion of the substrate. The backplate includes a plurality of acoustic holes. The backplate is disposed on one side of the diaphragm. An air gap is formed between the backplate and the diaphragm. The first protrusion extends from the backplate towards the air gap.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: March 26, 2024
    Assignee: FORTEMEDIA, INC.
    Inventors: Chih-Yuan Chen, Jien-Ming Chen, Feng-Chia Hsu, Wen-Shan Lin, Nai-Hao Kuo
  • Patent number: 11940060
    Abstract: The present invention provides a seal ring structure, which comprises a seal ring member. The seal ring member includes a first ring opening on one side and a second ring opening on the other. A periphery of the first ring opening includes a plurality of leak grooves. When the seal ring member and the valve ball squeeze each other, the plurality of leak grooves can reduce the torque required to rotate the valve ball. A leak-groove length of the plurality of leak grooves is smaller than a seal-ring-member length of the seal ring member. The plurality of leak grooves do not penetrate the seal ring member for avoiding leakage of fluid.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: March 26, 2024
    Assignee: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTRE
    Inventors: Ching-An Lin, Chin-Kang Chen, Chia-Ho Cheng
  • Patent number: 11942451
    Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Yen Chang, Yu-Chia Lai, Cheng-Shiuan Wong, Ting Hao Kuo, Ching-Hua Hsieh, Hao-Yi Tsai, Kuo-Lung Pan, Hsiu-Jen Lin
  • Patent number: 11942750
    Abstract: A laser inspection system is provided. A laser source emits a laser with a first spectrum and the laser is transmitted by a first optical fiber. A gain optical fiber doped with special ions is connected to the first optical fiber, and a light detector is provided around the gain optical fiber. When the laser with the first spectrum passes through the gain optical fiber, the gain optical fiber absorbs part of the energy level of the laser with the first spectrum, so that the laser with the first spectrum is converted to generate light with a second spectrum based on the frequency conversion phenomenon. The light detector detects the intensity of the light with the second spectrum, so that the power of the laser source can be obtained.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: March 26, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yi-Chi Lee, Hsin-Chia Su, Shih-Ting Lin, Yu-Cheng Song, Fu-Shun Ho, Chih-Chun Chen
  • Patent number: 11942550
    Abstract: A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chang Su, Yan-Ting Lin, Chien-Wei Lee, Bang-Ting Yan, Chih Teng Hsu, Chih-Chiang Chang, Chien-I Kuo, Chii-Horng Li, Yee-Chia Yeo
  • Publication number: 20240096806
    Abstract: A method for manufacturing a semiconductor structure is provided. A substrate including a fin structure is received, provided or formed. A sacrificial gate layer is formed over the fin structure and a source/drain structure is formed adjacent to the sacrificial gate layer, wherein the sacrificial gate layer is surrounded by a dielectric structure. The sacrificial gate layer is removed, wherein a recess is defined by the dielectric structure. A work function layer is formed in the recess, wherein the work function layer includes an overhang portion at an opening of the recess. A thickness of the work function layer is reduced. A glue layer is formed over the work function layer. A semiconductor structure thereof is also provided.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 21, 2024
    Inventors: CHAO-HSUAN CHEN, WEI CHEN HUNG, LI-WEI YIN, YU-HSIEN LIN, YIH-ANN LIN, RYAN CHIA-JEN CHEN
  • Publication number: 20240096705
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Publication number: 20240096630
    Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.
    Type: Application
    Filed: January 12, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Jih-Sheng Yang, Shih-Chieh Chao, Yih-Ann Lin, Ryan Chia-Jen Chen
  • Publication number: 20240097888
    Abstract: In a file sharing system, a key manager unit realizes a correspondence between the first user identifier and the first public key in response to a registration request of the first user, generates a first key material for encrypting the first file into a first encrypted file, and generates a first credential according to the first user identifier, the first file identifier, the first public key and the first key material after receiving an access-right claim request to the first file from the first user. A file storage unit stores the first encrypted file and the first credential. The first user uses the first user identifier, the first file identifier and the first private key to retrieve the first key material out of the first credential, and uses the first key material to decrypt the first encrypted file into the first file.
    Type: Application
    Filed: September 18, 2023
    Publication date: March 21, 2024
    Inventors: CHIA-JUNG LIANG, CHIHHUNG LIN, CHIH-PING HSIAO, YU-JIE SU, CHIA-HSIN CHENG, TUN-HOU WANG, MENG-CHAO TSAI, YUEH-CHIN LIN
  • Patent number: 11935793
    Abstract: A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11932087
    Abstract: A vanity mirror with lighting function includes: a mounting portion, connected to a vehicle sun visor; a movable portion which can move relatively to the mounting portion; a mirror located in the mounting portion or the movable portion; a power storage unit; a front-open sensing unit for determining whether the vanity mirror is in a front-open state or a folded state; a sensing circuit, wherein when the vanity mirror is in the front-open state, the power storage unit conducts electrical power to the sensing circuit; and a light source for providing lighting function, wherein in the front-open state, whether to emit light and intensity of the light is determined according to the sensing result of the sensing circuit.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: March 19, 2024
    Assignee: ZEALIO ELECTRONICS CO., LTD.
    Inventors: Chia-Pao Cheng, Pao-Lin Guo, An-Tsun Teng
  • Publication number: 20240087877
    Abstract: A backside metallized compound semiconductor device includes a compound semiconductor wafer and a metal layered structure. The compound semiconductor wafer includes a substrate having opposite front and back surfaces, and a ground pad structure formed on the front surface. The substrate is formed with a via extending from the back surface to the front surface to expose a side wall of the substrate and a portion of the ground pad structure. The metal layered structure is disposed on the back surface, and covers the side wall and the portion of the ground pad structure. The metal layered structure includes an adhesion layer, a seed layer, a gold layer, and an electroplated copper layer that are formed on the back surface in such order. The method for manufacturing the backside metallized compound semiconductor device is also disclosed.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Tsung-Te CHIU, Kechuang LIN, Houng-Chi WEI, Chia-Chu KUO, Bing-Han CHUANG
  • Publication number: 20240086633
    Abstract: A method for generating and outputting a message is implemented using an electronic device the stores a computer program product and a text database. The text database includes a main message template, a template text that includes a placeholder, and a word group that includes a plurality of preset words for replacing the placeholder. The method includes: in response to receipt of a command for execution of the computer program product, displaying an editing interface including the main message template; in response to receipt of user operation of a selection of the main message template, displaying the template text; in response to receipt of user operation of a selection of one of the preset words via the user interface, generating an edited text by replacing the placeholder with the one of the preset words in the template text; and outputting the edited text as a message.
    Type: Application
    Filed: April 25, 2023
    Publication date: March 14, 2024
    Inventors: Yi-Ru CHIU, Ting-Yi LI, Hong-Xun WANG, Jin-Lin CHEN, Chih-Hsuan YEH, Chia-Chi YIN, Wei-Ting LI, Po-Lun CHANG
  • Publication number: 20240088061
    Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Shu-Shen Yeh, Che-Chia Yang, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng, Chia-Hsiang Lin
  • Patent number: 11927312
    Abstract: The disclosure provides an electronic device, including a circuit board, multiple semiconductor components, a first light reflecting structure, and a second light reflecting structure. The circuit board includes a substrate, and the substrate may have a first surface and at least one side surface. The multiple semiconductor components are disposed on the first surface. The first light reflecting structure is disposed on the first surface. The second light reflecting structure is disposed on the first surface and the at least one side surface.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: March 12, 2024
    Assignee: Innolux Corporation
    Inventors: Chin-Chia Huang, Chieh-Ying Chen, Jia-Huei Lin, Chin-Tai Hsu, Tzu-Chien Huang, Fu-Sheng Tsai
  • Publication number: 20240077479
    Abstract: A detection system and method for the migrating cell is provided. The system is configured to detect a migrating cell combined with an immunomagnetic bead. The system includes a platform, a microchannel, a magnetic field source, a coherent light source and an optical sensing module. The microchannel is configured to allow the migrating cell to flow in it along a flow direction. The magnetic field source is configured to provide magnetic force to the migrating cell combined with the immunomagnetic bead. The magnetic force includes at least one magnetic force component and the magnetic force component is opposite to the flow direction of the microchannel. The coherent light source is configured to provide the microchannel with the coherent light. The optical sensing module is configured to receive the interference light caused by the coherent light being reflected by the sample inside the microchannel.
    Type: Application
    Filed: August 10, 2023
    Publication date: March 7, 2024
    Applicant: DeepBrain Tech. Inc
    Inventors: Han-Lin Wang, Chia-Wei Chen, Yao-Wen Liang, Ting-Chun Lin, Yun-Ting Kuo, You-Yin Chen, Yu-Chun Lo, Ssu-Ju Li, Ching-Wen Chang, Yi-Chen Lin
  • Publication number: 20240079787
    Abstract: An antenna structure includes a radiative antenna element disposed in a first conductive layer and a reference ground plane, disposed in a second conductive layer under the first conductive layer. The radiative antenna element is loaded with a plurality of slots and is electrically connected to the reference ground plane through a plurality of vias, and the vias are placed along a first line of the radiative antenna element and the slots are placed along a second line perpendicular to the first line.
    Type: Application
    Filed: August 14, 2023
    Publication date: March 7, 2024
    Applicant: MEDIATEK INC.
    Inventors: Debapratim Dhara, Shih-Chia Chiu, Yen-Ju Lu, Sheng-Mou Lin
  • Publication number: 20240081015
    Abstract: An electronic device includes a chassis casing, a device casing, a latch assembly, a bracket, and a rotating shaft assembly. The chassis casing includes a bottom plate. The device casing is detachably disposed in the chassis casing, and the device casing is provided with a stopper. The latch assembly is disposed at the chassis casing, and the latch assembly includes a sliding member. The bracket is disposed in the chassis casing and at an end of the device casing opposite to the latch assembly. The rotating shaft assembly is respectively connected to the device casing and the bracket. The device casing is adjustable between an installation position and an lifting position via the rotating shaft assembly. The sliding member of the latch assembly is used to fix the stopper, so that the device casing is located at the installation position.
    Type: Application
    Filed: November 4, 2022
    Publication date: March 7, 2024
    Inventors: Chia-Hsin Liu, Yu-Jian Wu, Wei Lin
  • Publication number: 20240079493
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a gate structure disposed on the substrate. The semiconductor device also includes a source region and a drain region disposed within the substrate. The substrate includes a drift region laterally extending between the source region and the drain region. The semiconductor device further includes a first stressor layer disposed over the drift region of the substrate. The first stressor layer is configured to apply a first stress to the drift region of the substrate. In addition, the semiconductor device includes a second stressor layer disposed on the first stressor layer. The second stressor layer is configured to apply a second stress to the drift region of the substrate, and the first stress is opposite to the second stress.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Inventors: GUAN-QI CHEN, CHEN CHI HSIAO, KUN-TSANG CHUANG, FANG YI LIAO, YU SHAN HUNG, CHUN-CHIA CHEN, YU-SHAN HUANG, TUNG-I LIN