Abstract: An electrostatic discharge (ESD) protection circuit coupled to an input pad comprises a diode formed in a substrate and coupled to the input pad; a P deep well formed in the substrate; an N well formed in the P deep well; a first P+ doped region in the N well; and an NMOS transistor formed on the substrate, comprising a gate, a source and a drain, wherein the drain is formed in the N well and coupled to a Vcc, and the source is formed in the P deep well; and a second P+ doped region formed in the P deep well. The ESD protection circuit uses a smaller area than the conventional ESD protection circuit.

Abstract: In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.

Abstract: In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.

Abstract: An ESD protection circuit is adapted for an integrated circuit with a first power source and a second power source. The ESD protection circuit comprises a first silicon controlled rectifier (SCR), and in some embodiments a second silicon controlled rectifier, and a parasitic diode. The silicon rectifiers as well as the parasitic diode can all be formed using a single well formed in a substrate. Further, the ESD protection circuit can be used in systems that have multiple power sources regardless of the difference in voltage between the power sources.

Abstract: An ESD protection circuit is adapted for an integrated circuit with a first power source and a second power source. The ESD protection circuit comprises a first silicon controlled rectifier (SCR), a second silicon controlled rectifier, and a parasitic diode. The gate of the first silicon controlled rectifier is coupled to a first power source, and the gate of the second silicon controlled rectifier is also coupled to the first power source line.

Abstract: An electro-static discharge (ESD) protection circuit for a dual polarity I/O pad is provided. The protection circuit includes a substrate of first type; a deep well region of second type disposed in the first type substrate; a well region of first type disposed in the second type deep well region; a first transistor disposed over the well region of first type, wherein the first transistor has a first source, a first gate and a first drain; a second transistor disposed over the substrate of first type, wherein the second transistor has a second source, a second gate and a second drain, and the second source is connected with the first drain, and both of them are disposed in a portion of the well region of first type, the deep well region of second type and the substrate of first type; a first doped region is disposed in the first type well region and laterally adjacent to the first source; a second doped region is disposed in the substrate of first type and laterally adjacent to the second drain.

Abstract: An electrostatic discharge (ESD) protection circuit coupled to an input pad comprises a diode formed in a substrate and coupled to the input pad; a P deep well formed in the substrate; an N well formed in the P deep well; a first P+ doped region in the N well; and an NMOS transistor formed on the substrate, comprising a gate, a source and a drain, wherein the drain is formed in the N well and coupled to a Vcc, and the source is formed in the P deep well; and a second P+ doped region formed in the P deep well. The ESD protection circuit uses a smaller area than the conventional ESD protection circuit.

Abstract: An electro-static discharge (ESD) protection circuit for a dual polarity I/O pad is provided. The protection circuit includes a substrate of first type; a deep well region of second type disposed in the first type substrate; a well region of first type disposed in the second type deep well region; a first transistor disposed over the well region of first type, wherein the first transistor has a first source, a first gate and a first drain; a second transistor disposed over the substrate of first type, wherein the second transistor has a second source, a second gate and a second drain, and the second source is connected with the first drain, and both of them are disposed in a portion of the well region of first type, the deep well region of second type and the substrate of first type; a first doped region is disposed in the first type well region and laterally adjacent to the first source; a second doped region is disposed in the substrate of first type and laterally adjacent to the second drain.

Abstract: In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.

Abstract: A package structure for a multi-chip integrated circuit (IC) is disclosed and the structure includes substrate having a position for bonding with chips for chip-bonding and having at least a hole for the passage of a gold wire in the course of wire-bonding, a first chip attached to the substrate with a chip bonding agent and being wire-bonded on the substrate and the chip bonding position being opposite to the 2nd chip with the substrate in-between, and the gold wire of the wire-bonding passed through the hole of the substrate from the substrate bonding pad at the substrate and on the same lateral side of the second chip and being connected to the pin pad of the first chip, at least a second chip being flip-chip bonded onto the substrate and the bonding position being at different sides of the bonding between the substrate and the first chip, and a package body including filler of the second chip extended to cover the hole of the substrate and the first chip and the gold wire connected to the substrate and th

Abstract: A fabrication method for solder bump pattern of rear section wafer package is disclosed and the method includes the steps of: (a) pattern-etching the wafer at a passivation layer for the positioning of the solder bump; (b) depositing the entire under bump metal layer,

Abstract: A method of wire bonding of a semiconductor device for resolving oxidation of copper bonding pad is disclosed. The method comprises the steps of exposing the copper bonding pad of a wafer which has been completed with semiconductor circuit fabrication; covering the copper bonding pad of the wafer with a protective anti-oxidization film which will be vaporized when heated; performing wire bonding directly without requiring the removal of the protective film, employing ultrasonic vibration energy, pressurizing deformation energy and heat energy in the course of bonding to vaporize the protective film so that the metal wire and the copper pad form a large area intermetallic compound layer for bonding.

Abstract: An open-typed multi-chip stack-packaging is disclosed and the packaging comprises a substrate having a first surface and a second surface, at least a through opening formed on the substrate, and including at least two layers of circuitry to electrically transmit signals; at least a first chip positioned on the upper section of the opening of the first surface and a plurality of protruded blocks being soldered onto the circuitry on the first surface of the substrate at the external region of the substrate for electrically connection; at least a second chip stacked onto the first chip and the second chip being connected electrically to the circuitry of the first surface with gold lines; at least a third chip positioned at the lower section of the opening of the second surface and having a size smaller than the first chip, and a plurality of protruded blocks being used to electrically bond with the center position of the first chip, and adhesive being used to fill the first chip and the third chip, and the regio