Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.

Abstract: Present disclosure provides a semiconductor structure, including a semiconductor fin having a first portion and a second portion over the first portion, a first conductive region abutting a first lateral surface of the first portion and a first lateral surface of the second portion, a metal gate having a bottom portion and an upper portion, the bottom portion being between the first portion and the second portion of the semiconductor fin, and the upper portion being over the second portion of the semiconductor fin, and a first spacer between the bottom portion of the metal gate and the first conductive region. A method for manufacturing the semiconductor structure described herein is also provided.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: A color mixing light system comprises a pyramidal mirror assembly comprising three or more mirrors constructed and arranged in a pyramid structure and three or more color light sources. The pyramidal mirror assembly divides the light beams from the color light sources so that a first portion is reflected by the mirrors and a second portion extends beyond the mirrors to collectively form a multicolor pattern comprising plurality of overlapping color regions on a surface.

Abstract: A color mixing light system comprises a pyramidal mirror assembly comprising three or more mirrors constructed and arranged in a pyramid structure and three or more color light sources. The pyramidal mirror assembly divides the light beams from the color light sources so that a first portion is reflected by the mirrors and a second portion extends beyond the mirrors to collectively form a multicolor pattern comprising plurality of overlapping color regions on a surface.

Abstract: A color mixing light system comprises a pyramidal mirror assembly comprising three or more mirrors constructed and arranged in a pyramid structure and three or more color light sources. The pyramidal mirror assembly divides the light beams from the color light sources so that a first portion is reflected by the mirrors and a second portion extends beyond the mirrors to collectively form a multicolor pattern comprising plurality of overlapping color regions on a surface.

Abstract: A color mixing light system comprises a pyramidal mirror assembly comprising three or more mirrors constructed and arranged in a pyramid structure and three or more color light sources. The pyramidal mirror assembly divides the light beams from the color light sources so that a first portion is reflected by the mirrors and a second portion extends beyond the mirrors to collectively form a multicolor pattern comprising plurality of overlapping color regions on a surface.

Abstract: Provided is a beam-steering mechanism, comprising a lens and a light source positioned in a focal plane of the lens. One of the light source and the lens moves relative to the other of the light source and the lens. The light source outputs a light beam at the lens which forms an illumination spot on a surface from the light beam. The illumination spot moves in a direction in response to a movement of one of the light source and the lens.

Abstract: A quantitative material supply mechanism: an accommodation bucket, a delivery device, an adjustment device, and a quantitative feeding bucket. The accommodation bucket includes an outlet defined on a bottom thereof. The delivery device includes a conveyor belt, a drive roller, a driven roller, and a driving unit. The driving unit is connected with the drive roller and drives the drive roller to rotate, and the drive roller matches with the driven roller to actuate the conveyor belt to rotate. The adjustment device is arranged above the conveyor belt and is located between the accommodation bucket and the turnaround portion. The adjustment device includes two adjusters and two actuation units opposite to the two adjusters respectively. The quantitative feeding bucket is mounted below the turnaround portion of the conveyor belt so as to hold the materials which are delivered by the conveyor belt and drop from the turnaround portion.

Abstract: A color mixing light system comprises a pyramidal mirror assembly comprising three or more mirrors constructed and arranged in a pyramid structure and three or more color light sources. The pyramidal mirror assembly divides the light beams from the color light sources so that a first portion is reflected by the minors and a second portion extends beyond the minors to collectively form a multicolor pattern comprising plurality of overlapping color regions on a surface.

Abstract: A multiple IC, buffered, image sensor has a first IC with pixels, selection transistors, and interconnect coupling selected pixels with first inter-die bond pads that convey image data to a second IC having logic and ADCs. The ADCs having inputs coupled to selected pixels and outputting through-silicon vias and inter-die bond pads to a third IC coupled to buffer raw image data in DRAM. A method includes capturing images with array pixel IC divided into sub-arrays each coupled to a separate, associated, ADC through inter-die bonds, scanning the sub-arrays and converting the image data to digital image data; and transferring the digital image data over inter-die bonds into buffers in DRAM.

Abstract: An image sensor has multiple blocks each with multiple pixels; each block uses a separate analog-to-digital converter (ADC). The ADCs feed digitized images into an image DRAM, and the image DRAM feeds digitized images to an alignment buffer in turn providing images to an image processor. The ADCs feed digitized image data into the image DRAM in hyperlong words, using staggered, overlapping, word lines to write each hyperlong word. A method of imaging includes exposing a photosensor array to light, reading pixels of the array in sequence within each block of pixels, one pixel in each block simultaneously; and digitizing pixels in separate ADCs for each block. Digitized pixels are written to image DRAM as hyperlong words with one pixel from each block in parallel using staggered, overlapping, word lines. Pixels are read from the image DRAM into an alignment buffer and thence to the image processor.

Abstract: An anti-reflective integrated touch display panel includes an anti-reflective structure and touch electrodes. The anti-reflective structure includes a first insulating layer, a second insulating layer disposed on the first insulating layer, a conducting layer disposed on the second insulating layer, a third insulating layer disposed on the second insulating layer, and a fourth insulating layer disposed on the third insulating layer. The first insulating layer includes silicon oxide or silicon nitride, and has a thickness of 0.1 to 2 micrometers. The second insulating layer includes silicon oxide or strontium oxide, and has a thickness of 0.001 to 0.1 micrometer. The conducting layer includes molybdenum, and has a thickness of 0.01 to 0.05 micrometer. The fourth insulating layer includes silicon nitride, and has a thickness of 0.001 to 0.3 micrometer. The touch electrodes are disposed between the third insulating layer and the fourth insulating layer.

Abstract: A bond-per-pixel-block image sensor has a pixel array including multiple pixel blocks with selection circuitry to couple signals to an ADC. The image sensor has an image RAM of DRAM superblocks, each superblock with multiple DRAM blocks each having tristate output driving an image RAM output bus, and data input from several of the ADCs. Each DRAM block has an address multiplexor coupled to read and write addresses. DRAM blocks of each superblock are written simultaneously with data wider than a width of the image RAM output bus. A method of capturing and processing images includes reading a first image frame from pixels of a pixel block through ADCs; writing digital pixel data for the first image frame in a first DRAM superblock; and reading pixel data into an alignment buffer. The method includes overlapping reading the first image frame with writing a second image frame into a second superblock.

Abstract: An image sensor has multiple blocks each with multiple pixels; each block uses a separate analog-to-digital converter (ADC). The ADCs feed digitized images into an image DRAM, and the image DRAM feeds digitized images to an alignment buffer in turn providing images to an image processor. The ADCs feed digitized image data into the image DRAM in hyperlong words, using staggered, overlapping, word lines to write each hyperlong word. A method of imaging includes exposing a photosensor array to light, reading pixels of the array in sequence within each block of pixels, one pixel in each block simultaneously; and digitizing pixels in separate ADCs for each block. Digitized pixels are written to image DRAM as hyperlong words with one pixel from each block in parallel using staggered, overlapping, word lines. Pixels are read from the image DRAM into an alignment buffer and thence to the image processor.

Abstract: In a system, a 1T DRAM a decoder drives word lines, each driving enable transistors of true and complement DRAM cells; true DRAM cells being coupled to true bit lines, with complement DRAM cells coupled to complement bit lines. Differential sense amplifiers each receive true and complement bit lines. In a method of writing and reading DRAM, a DRAM is provided with common word lines feeding true and complement cells attached to true and complement bit lines. Writing the DRAM includes applying data to true bit lines with complement data on complement bit lines; then pulsing a selected word line to write data into true and complement cells. Reading requires pulsing precharge lines to reset true and complement bit lines; selecting a single word line to read the true and complement cells onto true and complement bit lines; and sensing differences between true and complement bit lines.

Abstract: A multiple IC, buffered, image sensor has a first IC with pixels, selection transistors, and interconnect coupling selected pixels with first inter-die bond pads that convey image data to a second IC having logic and ADCs. The ADCs having inputs coupled to selected pixels and outputting through-silicon vias and inter-die bond pads to a third IC coupled to buffer raw image data in DRAM. A method includes capturing images with array pixel IC divided into sub-arrays each coupled to a separate, associated, ADC through inter-die bonds, scanning the sub-arrays and converting the image data to digital image data; and transferring the digital image data over inter-die bonds into buffers in DRAM.

Abstract: An anti-reflective integrated touch display panel includes an anti-reflective structure and touch electrodes. The anti-reflective structure includes a first insulating layer, a second insulating layer disposed on the first insulating layer, a conducting layer disposed on the second insulating layer, a third insulating layer disposed on the second insulating layer, and a fourth insulating layer disposed on the third insulating layer. The first insulating layer includes silicon oxide or silicon nitride, and has a thickness of 0.1 to 2 micrometers. The second insulating layer includes silicon oxide or strontium oxide, and has a thickness of 0.001 to 0.1 micrometer. The conducting layer includes molybdenum, and has a thickness of 0.01 to 0.05 micrometer. The fourth insulating layer includes silicon nitride, and has a thickness of 0.001 to 0.3 micrometer. The touch electrodes are disposed between the third insulating layer and the fourth insulating layer.