Patents by Inventor CHIA-PANG KUO
CHIA-PANG KUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240006234Abstract: A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.Type: ApplicationFiled: August 2, 2023Publication date: January 4, 2024Inventors: Chia-Pang Kuo, Ya-Lien Lee, Chieh-Yi Shen
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Patent number: 11837500Abstract: A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.Type: GrantFiled: June 30, 2022Date of Patent: December 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Pang Kuo, Ya-Lien Lee, Chieh-Yi Shen
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Publication number: 20230369224Abstract: A structure includes a first conductive feature in a first dielectric layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature includes a metal adhesion layer over and physically contacting the first conductive feature; a barrier layer extending along sidewalls of the second dielectric layer; and a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends between the barrier layer and the metal adhesion layer.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Inventors: Chia-Pang Kuo, Chih-Yi Chang, Ming-Hsiao Hsieh, Wei-Hsiang Chan, Ya-Lien Lee, Chien Chung Huang, Chun-Chieh Lin, Hung-Wen Su
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Patent number: 11810857Abstract: A structure includes a first conductive feature in a first dielectric layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature includes a metal adhesion layer over and physically contacting the first conductive feature; a barrier layer extending along sidewalls of the second dielectric layer; and a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends between the barrier layer and the metal adhesion layer.Type: GrantFiled: August 25, 2020Date of Patent: November 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Pang Kuo, Chih-Yi Chang, Ming-Hsiao Hsieh, Wei-Hsiang Chan, Ya-Lien Lee, Chien Chung Huang, Chun-Chieh Lin, Hung-Wen Su
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Publication number: 20230299002Abstract: Various back end of line (BEOL) layer formation techniques described herein enable reduced contact resistance, reduced surface roughness, and/or increased semiconductor device performance for BEOL layers such as interconnects and/or metallization layers.Type: ApplicationFiled: March 18, 2022Publication date: September 21, 2023Inventors: Shu-Cheng CHIN, Chih-Chien CHI, Hsin-Ying PENG, Jau-Jiun HUANG, Ya-Lien LEE, Kuan-Chia CHEN, Chia-Pang KUO, Yao-Min LIU
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Patent number: 11676898Abstract: A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.Type: GrantFiled: June 11, 2020Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Pang Kuo, Huan-Yu Shih, Wen-Hsuan Chen, Cheng-Lun Tsai, Ya-Lien Lee, Cheng-Hui Weng, Chun-Chieh Lin, Hung-Wen Su, Yao-Min Liu
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Publication number: 20230042277Abstract: A semiconductor processing tool performs passivation layer deposition and removal in situ. A transport mechanism included in the semiconductor processing tool transfers a semiconductor structure through different deposition chambers (e.g., without breaking or removing a vacuum environment). Accordingly, the semiconductor processing tool deposits a target layer that is thinner on, or even absent from, a metal layer, such that contact resistance is reduced between a conductive structure formed over the target layer and the metal layer. As a result, electrical performance of a device including the conductive structure is improved. Moreover, because the process is performed in situ (e.g., without breaking or removing the vacuum) in the semiconductor processing tool, production time and risk of impurities in the conductive structure are reduced. As a result, throughput is increased, and chances of spoiled wafers are decreased.Type: ApplicationFiled: March 7, 2022Publication date: February 9, 2023Inventors: Chia-Pang KUO, Yao-Min LIU, Shu-Cheng CHIN, Chih-Chien CHI, Cheng-Hui WENG
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Patent number: 11527476Abstract: A semiconductor structure and a method of forming the same are provided. A method includes depositing a dielectric layer over a conductive feature. The dielectric layer is patterned to form an opening therein. The opening exposes a first portion of the conductive feature. A first barrier layer is deposited on a sidewall of the opening. The first portion of the conductive feature remains exposed at the end of depositing the first barrier layer.Type: GrantFiled: January 7, 2021Date of Patent: December 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yao-Min Liu, Chia-Pang Kuo, Chien Chung Huang, Chih-Yi Chang, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai
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Publication number: 20220367376Abstract: A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Inventors: Chia-Pang Kuo, Huan-Yu Shih, Wen-Hsuan Chen, Cheng-Lun Tsai, Ya-Lien Lee, Cheng-Hui Weng, Chun-Chieh Lin, Hung-Wen Su, Yao-Min Liu
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Publication number: 20220328347Abstract: A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.Type: ApplicationFiled: June 30, 2022Publication date: October 13, 2022Inventors: Chia-Pang Kuo, Ya-Lien Lee, Chieh-Yi Shen
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Patent number: 11398406Abstract: A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.Type: GrantFiled: December 7, 2018Date of Patent: July 26, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Pang Kuo, Ya-Lien Lee, Chieh-Yi Shen
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Publication number: 20220165616Abstract: A method includes forming a first conductive feature in a first dielectric layer. A second dielectric layer is formed over the first conductive feature and the first dielectric layer. An opening is formed in the second dielectric layer. The opening exposes a top surface of the first conductive feature. The top surface of the first conductive feature includes a first metallic material and a second metallic material different from the first metallic material. A native oxide layer is removed from the top surface of the first conductive feature. A surfactant soaking process is performed on the top surface of the first conductive feature. The surfactant soaking process forms a surfactant layer over the top surface of the first conductive feature. A first barrier layer is deposited on a sidewall of the opening. The surfactant layer remains exposed at the end of depositing the first barrier layer.Type: ApplicationFiled: February 11, 2022Publication date: May 26, 2022Inventors: Yao-Min Liu, Chia-Pang Kuo, Shu-Cheng Chin, Chih-Chien Chi, Cheng-Hui Weng, Hung-Wen Su, Ming-Hsing Tsai
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Publication number: 20220084937Abstract: A semiconductor structure and a method of forming the same are provided. A method includes depositing a dielectric layer over a conductive feature. The dielectric layer is patterned to form an opening therein. The opening exposes a first portion of the conductive feature. A first barrier layer is deposited on a sidewall of the opening. The first portion of the conductive feature remains exposed at the end of depositing the first barrier layer.Type: ApplicationFiled: January 7, 2021Publication date: March 17, 2022Inventors: Yao-Min Liu, Chia-Pang Kuo, Chien Chung Huang, Chih-Yi Chang, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai
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Publication number: 20220068826Abstract: A structure includes a first conductive feature in a first dielectric layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature includes a metal adhesion layer over and physically contacting the first conductive feature; a barrier layer extending along sidewalls of the second dielectric layer; and a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends between the barrier layer and the metal adhesion layer.Type: ApplicationFiled: August 25, 2020Publication date: March 3, 2022Inventors: Chia-Pang Kuo, Chih-Yi Chang, Ming-Hsiao Hsieh, Wei-Hsiang Chan, Ya-Lien Lee, Chien Chung Huang, Chun-Chieh Lin, Hung-Wen Su
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Publication number: 20210391275Abstract: A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.Type: ApplicationFiled: June 11, 2020Publication date: December 16, 2021Inventors: Chia-Pang Kuo, Huan-Yu Shih, Wen-Hsuan Chen, Cheng-Lun Tsai, Ya-Lien Lee, Cheng-Hui Weng, Chun-Chieh Lin, Hung-Wen Su, Yao-Min Liu
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Patent number: 11183424Abstract: Embodiments described herein relate generally to one or more methods for forming a barrier layer for a conductive feature in semiconductor processing. In some embodiments, an opening is formed through a dielectric layer to a conductive feature. A barrier layer is formed in the opening along a sidewall of the dielectric layer and on a surface of the conductive feature. Forming the barrier layer includes depositing a layer including using a precursor gas. The precursor gas has a first incubation time for deposition on the surface of the conductive feature and has a second incubation time for deposition on the sidewall of the dielectric layer. The first incubation time is greater than the second incubation time. A conductive fill material is formed in the opening and on the barrier layer.Type: GrantFiled: November 12, 2019Date of Patent: November 23, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Pang Kuo, Ya-Lien Lee
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Patent number: 11043413Abstract: Embodiments described herein relate generally to one or more methods for forming a barrier layer for a conductive feature in semiconductor processing. In some embodiments, an opening is formed through a dielectric layer to a conductive feature. A barrier layer is formed in the opening along a sidewall of the dielectric layer and on a surface of the conductive feature. Forming the barrier layer includes depositing a layer including using a precursor gas. The precursor gas has a first incubation time for deposition on the surface of the conductive feature and has a second incubation time for deposition on the sidewall of the dielectric layer. The first incubation time is greater than the second incubation time. A conductive fill material is formed in the opening and on the barrier layer.Type: GrantFiled: November 12, 2019Date of Patent: June 22, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Pang Kuo, Ya-Lien Lee
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Patent number: 11043416Abstract: A method for forming a semiconductor device includes forming a barrier layer over a dielectric layer, a concentration of an impurity in the barrier layer increasing as the barrier layer extends away from the dielectric layer; and performing a plasma process to treat the barrier layer.Type: GrantFiled: May 20, 2020Date of Patent: June 22, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Pang Kuo, Ya-Lien Lee
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Publication number: 20200279771Abstract: A method for forming a semiconductor device includes forming a barrier layer over a dielectric layer, a concentration of an impurity in the barrier layer increasing as the barrier layer extends away from the dielectric layer; and performing a plasma process to treat the barrier layer.Type: ApplicationFiled: May 20, 2020Publication date: September 3, 2020Inventors: Chia-Pang Kuo, Ya-Lien Lee
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Patent number: 10741442Abstract: Embodiments described herein relate generally to one or more methods for forming a barrier layer for a conductive feature in semiconductor processing. In some embodiments, an opening is formed through a dielectric layer to a conductive feature. A barrier layer is formed in the opening along a sidewall of the dielectric layer and on a surface of the conductive feature. Forming the barrier layer includes depositing a layer including using a precursor gas. The precursor gas has a first incubation time for deposition on the surface of the conductive feature and has a second incubation time for deposition on the sidewall of the dielectric layer. The first incubation time is greater than the second incubation time. A conductive fill material is formed in the opening and on the barrier layer.Type: GrantFiled: May 31, 2018Date of Patent: August 11, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Pang Kuo, Ya-Lien Lee