Abstract: A method for forming a semiconductor device includes forming a barrier layer over a dielectric layer, a concentration of an impurity in the barrier layer increasing as the barrier layer extends away from the dielectric layer; and performing a plasma process to treat the barrier layer.

Abstract: A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

Abstract: Embodiments described herein relate generally to one or more methods for forming a barrier layer for a conductive feature in semiconductor processing. In some embodiments, an opening is formed through a dielectric layer to a conductive feature. A barrier layer is formed in the opening along a sidewall of the dielectric layer and on a surface of the conductive feature. Forming the barrier layer includes depositing a layer including using a precursor gas. The precursor gas has a first incubation time for deposition on the surface of the conductive feature and has a second incubation time for deposition on the sidewall of the dielectric layer. The first incubation time is greater than the second incubation time. A conductive fill material is formed in the opening and on the barrier layer.

Abstract: Embodiments described herein relate generally to one or more methods for forming a barrier layer for a conductive feature in semiconductor processing. In some embodiments, an opening is formed through a dielectric layer to a conductive feature. A barrier layer is formed in the opening along a sidewall of the dielectric layer and on a surface of the conductive feature. Forming the barrier layer includes depositing a layer including using a precursor gas. The precursor gas has a first incubation time for deposition on the surface of the conductive feature and has a second incubation time for deposition on the sidewall of the dielectric layer. The first incubation time is greater than the second incubation time. A conductive fill material is formed in the opening and on the barrier layer.

Abstract: A method for forming a semiconductor device includes forming a barrier layer over a dielectric layer, a concentration of an impurity in the barrier layer increasing as the barrier layer extends away from the dielectric layer; and performing a plasma process to treat the barrier layer.

Abstract: Embodiments described herein relate generally to one or more methods for forming a barrier layer for a conductive feature in semiconductor processing. In some embodiments, an opening is formed through a dielectric layer to a conductive feature. A barrier layer is formed in the opening along a sidewall of the dielectric layer and on a surface of the conductive feature. Forming the barrier layer includes depositing a layer including using a precursor gas. The precursor gas has a first incubation time for deposition on the surface of the conductive feature and has a second incubation time for deposition on the sidewall of the dielectric layer. The first incubation time is greater than the second incubation time. A conductive fill material is formed in the opening and on the barrier layer.

Abstract: A solar cell includes a semiconductor substrate, a passivation layer, a back electrode layer, and several bus bars. The semiconductor substrate has an upper surface and a lower surface opposite with each other. The passivation layer is disposed at the lower surface and includes several blank regions and several first openings. Each first opening is not located in the blank regions. The bus bars are respectively disposed on the blank regions of the passivation layer. The back electrode layer is disposed on the passivation layer and electrically connected to the semiconductor substrate through the first openings. The back electrode layer includes several second openings corresponding to the bus bars, respectively. The size of each second opening is not greater than the size of the corresponding bus bar, so that the back electrode layer is electrically connected to the bus bars.

Abstract: A solar cell with high-reflectivity region and narrow etch mark is disclosed. The solar cell includes a semiconductor substrate having a first surface and a second surface, a low-reflectivity region in and on the semiconductor substrate, and an annular etch mark disposed on the first surface and surrounding the low-reflectivity region. The etch mark is located along the perimeter of the first surface and has an average width that is not greater than 2 mm. The second surface is a surface with high reflectivity.

Abstract: A solar cell includes a semiconductor substrate, a passivation layer, a back electrode layer, and several bus bars. The semiconductor substrate has an upper surface and a lower surface opposite with each other. The passivation layer is disposed at the lower surface and includes several blank regions and several first openings. Each first opening is not located in the blank regions. The bus bars are respectively disposed on the blank regions of the passivation layer. The back electrode layer is disposed on the passivation layer and electrically connected to the semiconductor substrate through the first openings. The back electrode layer includes several second openings corresponding to the bus bars, respectively. The size of each second opening is not greater than the size of the corresponding bus bar, so that the back electrode layer is electrically connected to the bus bars.

Abstract: A solar cell includes a semiconductor substrate with a first surface and a second surface, a doped emitter layer on the first surface, at least one front anti-reflection coating (ARC) on the first surface, a front electrode on the front ARC, a passivation layer on the second surface, a first rear ARC on the passivation layer, a second rear ARC on the first rear ARC, a third rear ARC on the second rear ARC, and a rear electrode on the third rear ARC. The first rear ARC has a refractive index that is smaller than 2.1, while the second rear ARC has a refractive index that is greater than or equal to 2.1. The second rear ARC has a refractive index that is greater than that of the third rear ARC.