Abstract: A method of manufacturing a package structure is provided. The method of manufacturing a package structure comprises receiving a first semiconductor structure and a second semiconductor structure; forming an isolation layer on each semiconductor structure; forming at least one supporting structure and at least one pad trench in the isolation layer; filling the pad trench with electrically conductive material; planarizing the isolation layer and the electrically conductive material to form bonding pads in a bonding layer on each semiconductor structure; and bonding the semiconductor structures.

Abstract: A high-insulation multilayer planar transformer (1) includes a pair of iron cores (20) and a circuit board integration (10a). The circuit board integration (10a) is stacked between the iron cores (20) and has a through hole (100a). The circuit board integration (10a) includes a first to a third insulating layers (11a, 12a, 14a) and a first to a second coil windings (13a, 15a). The first and third insulating layers (11a, 14a) include at least two insulating plates (111a, 141a) stacked with each other respectively. The second insulating layer (12a) includes at least one insulating plate (121a). The coil winding (13a, 15a) is disposed between the adjacent insulating layers and surrounds the through hole (100a) planarly. Therefore, the reinforced insulation requirement of safety regulations may be achieved.

Abstract: A method of using a coupling system includes aligning an optical fiber with a cavity in a chip, wherein aligning the optical fiber comprises orienting the fiber within an angle ranging from about 88-degrees to about 92-degrees with respect to a top surface of the chip. The method further includes emitting an optical signal from the optical fiber. The method further includes redirecting the optical signal into a waveguide using a grating positioned on an opposite side of the cavity from the optical fiber.

Abstract: A package comprises an interposer, comprising an interposer substrate including at least one layer, and a plurality of RDLs formed through at least a portion of the interposer substrate. The package also includes a die device structure comprising at least one device die, and a first test line (TL) structure interposed between the interposer and the die device structure. The first TL structure includes at least one first test line electrically coupled to the at least one device die, at least a portion of the at least one first test line extending beyond a peripheral edge of the die device structure to provide an electrical interface with the at least one device die.

Abstract: A method of making a photonic device includes depositing a cladding layer over a silicon layer. The method further includes patterning the cladding layer to expose a first portion of the silicon layer, wherein a second portion of the silicon layer is covered by the patterned cladding layer, and a waveguide portion is in the second portion of the silicon layer. The method further includes depositing a low refractive index layer directly over the patterned cladding layer, wherein a refractive index of the low refractive index layer is less than a refractive index of silicon nitride.

Abstract: A semiconductor device includes a first semiconductor die that operates at a first power, a second semiconductor die that is formed in a stack on the first semiconductor die and operates at a second power different than the first power, and a power management semiconductor die that is formed in the stack and provides the first power to the first semiconductor die through a first via and provides the second power to the second semiconductor die through a second via.

Abstract: A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.

Abstract: A semiconductor package includes a first connection die including a semiconductor substrate and an interconnect structure, and a first die stack disposed on the first connection die and including stacked dies, each of the stacked dies including a semiconductor substrate and an interconnect structure including a first connection line that is electrically connected to the interconnect structure of the first connection die. An angle formed between a plane of the first connection die and a plane of each stacked die ranges from about 45° to about 90°.

Abstract: A semiconductor device with dummy and active pixel structures and a method of fabricating the same are disclosed. The semiconductor device includes a first pixel region with a first pixel structure, a second pixel region, surrounding the first pixel region, includes a second pixel structure adjacent to the first pixel structure and electrically isolated from the first pixel structure, and a contact pad region with a pad structure disposed adjacent to the second pixel region. The first pixel structure includes a first epitaxial structure disposed within a substrate and a first capping layer disposed on the first epitaxial structure. The second pixel structure includes a second epitaxial structure disposed within the substrate and a second capping layer disposed on the second epitaxial structure. Top surfaces of the first and second epitaxial structures are substantially coplanar with each other. The first and second epitaxial structures includes a same semiconductor material.

Abstract: A semiconductor package includes: a first die; a second die stacked on an upper surface of the first die, the second die including a second semiconductor substrate and a second seal ring structure that extends along a perimeter of the second semiconductor substrate; a third die stacked on the upper surface of the first die, the third die including a third semiconductor substrate and a third seal ring structure that extends along a perimeter of the third semiconductor substrate; and a connection circuit that extends through the second seal ring structure and the third seal ring structure, in a lateral direction perpendicular to the stacking direction of the first die and the second die, to electrically connect the second semiconductor substrate and the third semiconductor substrate.

Abstract: A coupling system includes an optical fiber configured to carry an optical signal. The coupling system further includes a grating on a first side of a semiconductor layer, wherein the grating is configured to receive the optical signal. The coupling system further includes an interconnect structure over the grating on the first side of the semiconductor layer, wherein the interconnect structure defines a cavity aligned with the grating. The coupling system further includes a first polysilicon layer on a second side of the semiconductor layer, wherein the second side of the semiconductor layer is opposite to the first side of the semiconductor layer.

Abstract: A three-dimensional device structure includes a first die including a first semiconductor substrate, a second die disposed on the first die and including a second semiconductor substrate, a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second die, a redistribution layer structure disposed on the second die and the DE layer, and an integrated passive device (IPD) formed within in the DE layer and electrically connected to the first die and the redistribution layer structure.

Abstract: A semiconductor device with dummy and active pixel structures and a method of fabricating the same are disclosed. The semiconductor device includes a first pixel region with a first pixel structure, a second pixel region, surrounding the first pixel region, includes a second pixel structure adjacent to the first pixel structure and electrically isolated from the first pixel structure, and a contact pad region with a pad structure disposed adjacent to the second pixel region. The first pixel structure includes a first epitaxial structure disposed within a substrate and a first capping layer disposed on the first epitaxial structure. The second pixel structure includes a second epitaxial structure disposed within the substrate and a second capping layer disposed on the second epitaxial structure. Top surfaces of the first and second epitaxial structures are substantially coplanar with each other. The first and second epitaxial structures includes a same semiconductor material.

Abstract: A semiconductor die includes a first semiconductor substrate; a first interconnect structure disposed on a front side of the first semiconductor substrate; a first through-substrate via (TSV) structure extending through the first semiconductor substrate; and a first fuse structure disposed between and electrically connecting the TSV structure and the first interconnect structure.

Abstract: A method includes forming a plurality of openings extending into a substrate from a front surface of the substrate. The substrate includes a first semiconductor material. Each of the plurality of openings has a curve-based bottom surface. The method includes filling the plurality of openings with a second semiconductor material. The second semiconductor material is different from the first semiconductor material. The method includes forming a plurality of pixels that are configured to sense light in the plurality of openings, respectively, using the second semiconductor material.

Abstract: A three-dimensional device structure includes a first die, a second die disposed on the first die, and a connection circuit. The first die includes a first semiconductor substrate, a first interconnect structure disposed on the first semiconductor substrate, and a first seal ring surrounding the interconnect structure. The second die includes a second semiconductor substrate, a second interconnect structure disposed on the second semiconductor substrate, and a second seal ring surrounding the interconnect structure. The first connection circuit electrically couples the first seal ring to the second seal ring to provide an electrostatic discharge path.

Abstract: A die includes: a semiconductor substrate; an interconnect structure disposed on the semiconductor substrate and including: inter-metal dielectric (IMD) layers; metal features embedded in the IMD layers; and a guard ring structure including concentric first and second guard rings that extend through at least a subset of the IMD layers; and a through silicon via (TSV) structure extending through the semiconductor substrate and the subset of IMD layers to electrically contact one of the metal features. The first guard ring surrounds the TSV structure; and the second guard ring surrounds the first guard ring and is configured to reduce a parasitic capacitance between the guard ring structure and the TSV structure.

Abstract: A method for forming a semiconductor structure includes receiving a die; forming a dielectric layer to surround the die; removing a portion of the dielectric layer to form a first recess; disposing a first light blocking layer within the first recess; applying a dielectric paste over the first light blocking layer; removing a portion of the dielectric paste to form a second recess; disposing a second light blocking layer within the second recess; disposing a photoelectric device over the first light blocking layer and the second light blocking layer; forming a redistribution layer over the die, the dielectric layer and the photoelectric device; removing a portion of the redistribution layer to form a third recess over the photoelectric device; and coupling a light-conducting member to the photoelectric device through the third recess; wherein the second light blocking layer is separated from the first light blocking layer and the photoelectric device.

Abstract: A three-dimensional device structure includes a first die including a first semiconductor substrate, a second die disposed on the first die and including a second semiconductor substrate, a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second die, a redistribution layer structure disposed on the second die and the DE layer, and an integrated passive device (IPD) embedded in the DE layer and electrically connected to the first die and the redistribution layer structure.

Abstract: A moat trench laterally surrounding a device region is formed in a substrate. A conductive metallic substrate enclosure structure is formed in the moat trench. Deep trenches are formed in the substrate, and a trench capacitor structure is formed in the deep trenches. The substrate may be thinned by removing a backside portion of the substrate. A backside surface of the conductive metallic substrate enclosure structure is physically exposed. A backside metal layer is formed on a backside surface of the substrate and a backside surface of the conductive metallic substrate enclosure structure. A metallic interconnect enclosure structure and a metallic cap plate may be formed to provide a metallic shield structure configured to block electromagnetic radiation from impinging into the trench capacitor structure.