Patents by Inventor Chia-Ping Lai

Chia-Ping Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230369294
    Abstract: An array of complementary die sets is attached to a carrier substrate. A continuous complementary-level molding compound layer is formed around the array of complementary die sets. An array of primary semiconductor dies is attached to the array of complementary die sets. A continuous primary-level molding compound layer is formed around the array of primary semiconductor dies. The bonded assembly is diced by cutting along directions that are parallel to edges of the primary semiconductor dies. The sidewalls of the complementary dies are azimuthally tilted relative to sidewalls of the primary semiconductor dies, or major crystallographic directions of a single crystalline material in the carrier substrate are azimuthally tilted relative to sidewalls of the primary semiconductor dies.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Jen-Yuan CHANG, Chia-Ping LAI
  • Publication number: 20230358959
    Abstract: A photonic device includes an optical coupler, a photodetector, a waveguide structure, a metal-dielectric stack, a contact, an interlayer dielectric layer, and a protection layer. The optical coupler, the photodetector, and the waveguide structure are over a substrate. The waveguide structure is laterally connected to the optical couple. A top of the waveguide structure is lower than a top of the optical coupler. The metal-dielectric stack is over the optical coupler, the photodetector, and the waveguide structure. The metal-dielectric stack has a hole above the optical coupler. The contact connects the photodetector to the metal-dielectric stack. The interlayer dielectric layer is below the metal-dielectric stack and surrounds the contact. The protection layer lines the hole of the metal-dielectric stack. A bottom surface of the protection layer is lower than a top surface of the contact.
    Type: Application
    Filed: July 14, 2023
    Publication date: November 9, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sui-Ying HSU, Yueh-Ying LEE, Chien-Ying WU, Chen-Hao HUANG, Chien-Chang LEE, Chia-Ping LAI
  • Publication number: 20230352427
    Abstract: A die includes: a semiconductor substrate; an interconnect structure disposed on the semiconductor substrate and including: inter-metal dielectric (IMD) layers; metal features embedded in the IMD layers; and a guard ring structure including concentric first and second guard rings that extend through at least a subset of the IMD layers; and a through silicon via (TSV) structure extending through the semiconductor substrate and the subset of IMD layers to electrically contact one of the metal features. The first guard ring surrounds the TSV structure; and the second guard ring surrounds the first guard ring and is configured to reduce a parasitic capacitance between the guard ring structure and the TSV structure.
    Type: Application
    Filed: June 21, 2023
    Publication date: November 2, 2023
    Inventors: Jen-Yuan CHANG, Chien-Chang LEE, Chia-Ping LAI
  • Patent number: 11784199
    Abstract: A semiconductor device includes: a photodiode formed in a substrate; and at least one transistor having a gate feature that comprises a first portion and a second portion coupled to an end of the first portion, the first portion disposed above and extending along a major surface of the substrate and the second portion extending from the major surface of the substrate into the substrate, wherein the photodiode and the at least one transistor at least partially form a pixel.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: October 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hsiang Hung, Chung-Chuan Tseng, Li-Hsin Chu, Chia-Ping Lai
  • Publication number: 20230317743
    Abstract: A semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes silicon. The second semiconductor structure is embedded in the first semiconductor structure, in which the second semiconductor structure has at least one convex portion and at least one concave portion. The convex portion and the concave portion are on at least one edge of the second semiconductor structure, and a shape of the concave portion includes rectangle, trapezoid, inverted trapezoid, or parallelogram. The second semiconductor structure includes germanium, elements of group III or group V, or combinations thereof. The convex portion of the second semiconductor structure has a top surface substantially coplanar with a top surface of the first semiconductor structure.
    Type: Application
    Filed: June 5, 2023
    Publication date: October 5, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zong-Jie WU, Chiao-Chi WANG, Chung-Chuan TSENG, Chia-Ping LAI
  • Patent number: 11776896
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a capacitor device within a recessed portion of a substrate. The recessed portion has sidewalls and a bottom surface below a top surface of the substrate. The semiconductor structure includes a dielectric material disposed below the capacitor device and within the recessed portion. The semiconductor structure includes a first conductive structure adjacent one or more of the sidewalls of the recessed portion. The first conductive structure may include a conductive portion of the substrate or a conductive material disposed within the recessed portion. The semiconductor structure includes a second conductive structure coupled to the first conductive structure, where the second conductive structure provides an electrical connection from the first conductive structure to a voltage source or a voltage drain.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: October 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Yuan Chang, Chia-Ping Lai, Chien-Chang Lee
  • Patent number: 11756955
    Abstract: A method of making a semiconductor device, includes: providing a first dielectric layer; sequentially forming a first metal layer, a dummy capacitor dielectric layer, and a second metal layer over the first dielectric layer; and using a single mask layer with two patterns to simultaneously recess two portions of the second metal layer so as to define a metal thin film of a resistor and a top metal plate of a capacitor.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hsiang Hung, Li-Hsin Chu, Chia-Ping Lai, Chung-Chuan Tseng
  • Patent number: 11740409
    Abstract: A photonic device includes an optical coupler, a waveguide structure, a metal-dielectric stack, and a protection layer. The optical coupler is over a semiconductor substrate. The waveguide structure is over the semiconductor substrate and laterally connected to the optical coupler. A top of the waveguide structure is lower than a top of the optical coupler. The metal-dielectric stack is over the optical coupler and the waveguide structure. The metal-dielectric stack has a hole above the optical coupler. The protection layer lines the hole of the metal-dielectric stack.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sui-Ying Hsu, Yueh-Ying Lee, Chien-Ying Wu, Chen-Hao Huang, Chien-Chang Lee, Chia-Ping Lai
  • Publication number: 20230261039
    Abstract: Capacitors for use in semiconductor devices including a plurality of first trenches in a first region of a substrate, the first trenches extending in a first direction, a plurality of second trenches in the first region of the substrate, the second trenches extending in a second direction other than the first direction, with the adjacent second trenches and first trenches cooperating to define protruding structures and island structures having an upper surface that is at or below a plane defined by a portion of an upper surface of a substrate surrounding the first region with a series of film pairs including a dielectric layer and a conductive layer formed in the first and second trenches and the protruding and island structures.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 17, 2023
    Inventors: Wen-Feng KUO, Chung-Chuan TSENG, Chia-Ping LAI
  • Patent number: 11728288
    Abstract: A die includes: a semiconductor substrate; an interconnect structure disposed on the semiconductor substrate and including: inter-metal dielectric (IMD) layers; metal features embedded in the IMD layers; and a guard ring structure including concentric first and second guard rings that extend through at least a subset of the IMD layers; and a through silicon via (TSV) structure extending through the semiconductor substrate and the subset of IMD layers to electrically contact one of the metal features. The first guard ring surrounds the TSV structure; and the second guard ring surrounds the first guard ring and is configured to reduce a parasitic capacitance between the guard ring structure and the TSV structure.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jen-Yuan Chang, Chien-Chang Lee, Chia-Ping Lai
  • Publication number: 20230246056
    Abstract: A semiconductor device with dummy and active pixel structures and a method of fabricating the same are disclosed. The semiconductor device includes a first pixel region with a first pixel structure, a second pixel region, surrounding the first pixel region, includes a second pixel structure adjacent to the first pixel structure and electrically isolated from the first pixel structure, and a contact pad region with a pad structure disposed adjacent to the second pixel region. The first pixel structure includes a first epitaxial structure disposed within a substrate and a first capping layer disposed on the first epitaxial structure. The second pixel structure includes a second epitaxial structure disposed within the substrate and a second capping layer disposed on the second epitaxial structure. Top surfaces of the first and second epitaxial structures are substantially coplanar with each other. The first and second epitaxial structures includes a same semiconductor material.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 3, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wei CHEN, Chung-Chuan Tseng, Chiao-Chi Wang, Chia-Ping Lai
  • Patent number: 11670650
    Abstract: A semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes silicon. The second semiconductor structure is embedded in the first semiconductor structure, in which the second semiconductor structure has at least one convex portion and at least one concave portion. The convex portion and the concave portion are on at least one edge of the second semiconductor structure, and a shape of the concave portion includes rectangle, trapezoid, inverted trapezoid, or parallelogram. The second semiconductor structure includes germanium, elements of group III or group V, or combinations thereof.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zong-Jie Wu, Chiao-Chi Wang, Chung-Chuan Tseng, Chia-Ping Lai
  • Patent number: 11626444
    Abstract: A semiconductor device with dummy and active pixel structures and a method of fabricating the same are disclosed. The semiconductor device includes a first pixel region with a first pixel structure, a second pixel region, surrounding the first pixel region, includes a second pixel structure adjacent to the first pixel structure and electrically isolated from the first pixel structure, and a contact pad region with a pad structure disposed adjacent to the second pixel region. The first pixel structure includes a first epitaxial structure disposed within a substrate and a first capping layer disposed on the first epitaxial structure. The second pixel structure includes a second epitaxial structure disposed within the substrate and a second capping layer disposed on the second epitaxial structure. Top surfaces of the first and second epitaxial structures are substantially coplanar with each other. The first and second epitaxial structures includes a same semiconductor material.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: April 11, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wei Chen, Chung-Chuan Tseng, Chiao-Chi Wang, Chia-Ping Lai
  • Patent number: 11626442
    Abstract: Various embodiments of the present disclosure are directed towards methods for forming an image sensor in which a device layer overlies and has a different semiconductor material than a substrate and in which the device layer has high crystalline quality. Some embodiments of the methods include: epitaxially growing the device layer on the substrate; patterning the device layer to form a trench dividing the device layer into mesa structures corresponding to pixels; forming an inter-pixel dielectric layer filling the trench and separating the mesa structures; and forming photodetectors in the mesa structures. Other embodiments of the methods include: depositing the inter-pixel dielectric layer over the substrate; patterning the inter-pixel dielectric layer to form cavities corresponding to the pixels; epitaxially growing the mesa structures in the cavities; and forming the photodetectors in the mesa structures.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: April 11, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chiao-Chi Wang, Chung-Chuan Tseng, Chia-Ping Lai, Szu-Chien Tseng, Yeh-Hsun Fang
  • Publication number: 20230093001
    Abstract: A method includes forming a plurality of openings extending into a substrate from a front surface of the substrate. The substrate includes a first semiconductor material. Each of the plurality of openings has a curve-based bottom surface. The method includes filling the plurality of openings with a second semiconductor material. The second semiconductor material is different from the first semiconductor material. The method includes forming a plurality of pixels that are configured to sense light in the plurality of openings, respectively, using the second semiconductor material.
    Type: Application
    Filed: November 28, 2022
    Publication date: March 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yeh-Hsun Fang, Chiao-Chi Wang, Chung-Chuan Tseng, Chia-Ping Lai
  • Publication number: 20230067714
    Abstract: A three-dimensional device structure includes a first die, a second die disposed on the first die, and a connection circuit. The first die includes a first semiconductor substrate, a first interconnect structure disposed on the first semiconductor substrate, and a first seal surrounding the interconnect structure. The second die includes a second semiconductor substrate, a second interconnect structure disposed on the second semiconductor substrate, and a second seal ring surrounding the interconnect structure. The first connection circuit electrically couples the first seal ring to the second seal ring to provide an electrostatic discharge path.
    Type: Application
    Filed: August 26, 2021
    Publication date: March 2, 2023
    Inventors: Jen-Yuan CHANG, Chien-Chang LEE, Chia-Ping LAI
  • Publication number: 20230060265
    Abstract: A die stack includes: a first die including a first semiconductor substrate; a first redistribution layer (RDL) structure disposed on a front surface of the first die and electrically connected to the first semiconductor substrate; a second die bonded to the front surface of the first die and including a second semiconductor substrate; a third die bonded to the front surface of the first die and including a third semiconductor substrate; a second RDL structure disposed on front surfaces of the second and third dies and electrically connected to the second and third semiconductor substrates; and a through dielectric via (TDV) structure extending between the second and third dies and electrically connected to the first RDL structure and second RDL structure. The second and third dies are disposed in a plane that extends perpendicular to a vertical stacking direction of the die stack.
    Type: Application
    Filed: August 28, 2021
    Publication date: March 2, 2023
    Inventors: Jen-Yuan Chang, Chia-Ping Lai, Chien-Chang Lee
  • Publication number: 20230069774
    Abstract: A deep trench capacitor includes at least one deep trench and a layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers and continuously extending over the top surface of a substrate and into each of the at least one deep trench. A contact-level dielectric layer overlies the substrate and the layer stack. Contact assemblies extend through the contact-level dielectric layer. A subset of the contact assemblies vertically extend through a respective metallic electrode layer. For example, a first contact assembly includes a first tubular insulating spacer that laterally surrounds a first contact via structure and contacts a cylindrical sidewall of a topmost metallic electrode layer.
    Type: Application
    Filed: August 28, 2021
    Publication date: March 2, 2023
    Inventors: Jen-Yuan CHANG, Chia-Ping Lai, Chien-Chang Lee
  • Publication number: 20230064550
    Abstract: A coupling system includes an optical fiber configured to carry an optical signal. The coupling system further includes a chip in optical communication with the optical fiber. An angle between the optical fiber and a top surface of the chip ranges from about 92-degrees to about 88-degrees. The chip includes a grating configured to receive the optical signal; and a waveguide, wherein the grating is configured to receive the optical signal and redirect the optical signal along the waveguide. ms.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Sui-Ying HSU, Yuehying LEE, Chien-Ying WU, Chen-Hao HUANG, Chien-Chang LEE, Chia-Ping LAI
  • Publication number: 20230061940
    Abstract: A coupling system includes an optical fiber configured to carry an optical signal. The coupling system further includes a chip in optical communication with the optical fiber. The chip includes a substrate. The chip further includes a grating on a first side of the substrate, wherein the grating is configured to receive the optical signal. The chip further includes an interconnect structure over the grating on the first side of the substrate, wherein the interconnect structure defines a cavity aligned with the grating. The chip further includes a first polysilicon layer on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Chen-Hao HUANG, Hau-Yan LU, Sui-Ying HSU, Yuehying LEE, Chien-Ying WU, Chien-Chang LEE, Chia-Ping LAI