Patents by Inventor Chia-Sheng Huang

Chia-Sheng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162833
    Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 16, 2024
    Inventors: Yi-Sheng CHANG, Cheng-Chan HSU, Chia-Wei CHU, Chun-Yu YANG, Deng-Cyun HUANG, Yi-Hsun CHIU, Chien-An LAI, Yu-Tai WANG, Chi-Shou HO, Zhi-Yuan WU, Ko-Wen LU
  • Patent number: 11985819
    Abstract: A memory device includes an anti-fuse cell array having a plurality of anti-fuse cells, each of the plurality of anti-fuse cells having a first transistor and a second transistor connected to the first transistor. A first terminal of the first transistor is connected to a bit line and the bit line is a buried rail formed in a substrate of the first transistor and the second transistor.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Meng-Sheng Chang, Chia-En Huang
  • Patent number: 11978509
    Abstract: A memory device includes a plurality of resistive random access memory (RRAM) cells commonly connected between a bit line (BL) and a source line (SL). Each of the RRAM cells includes a resistor, a first transistor, and a second transistor coupled to each other in series, with the resistor connected to the BL and the second transistor connected to the SL. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage, the first threshold voltage being less than the second threshold voltage.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Yih Wang
  • Patent number: 11964299
    Abstract: A method for manufacturing a golf ball having a multi-layered pattern is provided. Firstly, a semi-finished product of the golf ball is provided and includes a ball-shaped body and a base layer covering an outer surface of the ball-shaped body. Then, the semi-finished product of the golf ball is rotated at a predetermined rotation speed, and a color paint is applied to the semi-finished product of the golf ball by spraying from each of an upper position, a middle position, and a lower position. The multi-layered pattern includes an upper-layer pattern area, a mid-layer pattern area, and a lower-layer pattern area that are different in color from each other.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: April 23, 2024
    Assignee: FOREMOST GOLF MFG. LTD.
    Inventors: Chia-Sheng Huang, Chi-Ling Lin, Chia-Cheng Wu, Ching-Hsiang Liu
  • Patent number: 11963348
    Abstract: A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Geng-Cing Lin, Ze-Sian Lu, Meng-Sheng Chang, Chia-En Huang, Jung-Ping Yang, Yen-Huei Chen
  • Patent number: 11956947
    Abstract: An OTP memory cell is provided. The OTP memory cell includes: an antifuse transistor, wherein a gate terminal of the antifuse transistor is connected to a first word line having a first signal, and the antifuse transistor is selectable between a first state and a second state in response to the first signal; and a selection transistor connected between the antifuse transistor and a bit line, wherein a gate terminal of the selection transistor is connected to a second word line having a second signal, and the selection transistor is configured to provide access to the antifuse transistor in response to the second signal. A first terminal of the antifuse transistor is a vacancy terminal, and a second terminal of the antifuse transistor is connected to the selection transistor.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Sheng Chang, Chia-En Huang
  • Patent number: 11955201
    Abstract: A memory device includes a plurality of arrays coupled in parallel with each other. A first array of the plurality of arrays includes a first switch and a plurality of first memory cells that are arranged in a first column, a second switch and a plurality of second memory cells that are arranged in a second column, and at least one data line coupled to the plurality of first memory cells and the plurality of second memory cells. The second switch is configured to output a data signal from the at least one data line to a sense amplifier.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Yi-Ching Liu, Yih Wang
  • Patent number: 11950411
    Abstract: A semiconductor device includes a plurality of first nanostructures extending along a first lateral direction. The semiconductor device includes a first epitaxial structure and second epitaxial structure respectively coupled to ends of each of the plurality of first nanostructures along the first lateral direction. The semiconductor device includes a dielectric fin structure disposed immediately next to a sidewall of each of the plurality of first nanostructures facing a second lateral direction perpendicular to the first lateral direction. The semiconductor device includes a first gate structure wrapping around each of the plurality of first nanostructures except for the sidewalls of the first nanostructures. The semiconductor device includes a metal structure disposed above the first gate structure and coupled to one of the first or second epitaxial structure.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Sheng Chang, Chia-En Huang
  • Patent number: 11942155
    Abstract: A memory system includes a memory array comprising a plurality of memory cells. Each of the memory cells includes a first programming transistor, a second programming transistor, a first reading transistor coupled to the first programming transistor in series, and a second reading transistor coupled to the second programming transistor in series. The memory system includes an authentication circuit operatively coupled to the memory array. The authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells. The logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first programming transistor or second programming transistor.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Yih Wang
  • Publication number: 20240088246
    Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Yu-Ling Hsu, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang, Yong-Shiuan Tsair, Chia-Sheng Lin, Shih Kuang Yang
  • Publication number: 20240090210
    Abstract: A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Chun Chung Su, Wen-Hsing Hsieh
  • Publication number: 20240090209
    Abstract: A memory device includes a programming transistor and a reading transistor of an anti-fuse memory cell. The programming transistor includes first semiconductor nanostructures vertically spaced apart from one another, each of the first semiconductor nanostructures having a first width along a first lateral direction. The reading transistor includes second semiconductor nanostructures vertically spaced apart from one another, each of the second semiconductor nanostructures having a second width different from the first width along the second direction. The memory device also includes a first and a second gate metals. The first gate metal wraps around each of the first semiconductor nanostructures with a first gate dielectric disposed therein. The second gate metal wraps around each of the second semiconductor nanostructures with a second gate dielectric disposed therein.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Yi-Hsun Chiu, Yih Wang
  • Publication number: 20240071537
    Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 29, 2024
    Inventors: Meng-Sheng Chang, Chia-En Huang, Shao-Yu Chou, Yih Wang
  • Patent number: 11759812
    Abstract: An apparatus for manufacturing golf balls each having an exterior pattern includes a conveying device and a spraying device. The spraying device is disposed at one side of a first processing area. The conveying device is configured to convey a ball-shaped body into the first processing area along a predetermined path, and to rotate the ball-shaped body at a predetermined speed. The spraying device includes a first sprayer and a second sprayer. The first sprayer and the second sprayer are configured to apply a color paint to the ball-shaped body from each of an upper position and a lower position.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: September 19, 2023
    Assignee: FOREMOST GOLF MFG. LTD.
    Inventors: Chia-Sheng Huang, Chi-Ling Lin, Chia-Cheng Wu, Ching-Hsiang Liu
  • Publication number: 20230215837
    Abstract: A method and an apparatus for bonding semiconductor substrates are provided. The apparatus includes a first support configured to carry a first semiconductor substrate and a second semiconductor substrate bonded to each other, a gauging component embedded in the first support and comprising a fiducial pattern, and a first sensor disposed proximate to the gauging component, and configured to emit a light source towards the fiducial pattern of the gauging component.
    Type: Application
    Filed: March 15, 2023
    Publication date: July 6, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Jui Huang, Ching-Hua Hsieh, Chien-Ling Hwang, Chia-Sheng Huang
  • Patent number: 11631652
    Abstract: A method and an apparatus for bonding semiconductor substrates are provided. The method includes at least the following steps. A first position of a first semiconductor substrate on a first support is gauged by a gauging component embedded in the first support and a first sensor facing towards the gauging component. A second semiconductor substrate is transferred to a position above the first semiconductor substrate by a second support. A second position of the second semiconductor substrate is gauged by a second sensor mounted on the second support and located above the first support. The first semiconductor substrate is positioned based on the second position of the second semiconductor substrate. The second semiconductor substrate is bonded to the first semiconductor substrate.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: April 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ying-Jui Huang, Ching-Hua Hsieh, Chien-Ling Hwang, Chia-Sheng Huang
  • Patent number: 11571708
    Abstract: A method for manufacturing a golf ball having a non-uniform dot pattern is provided. Firstly, a semi-finished product of a golf ball is provided, which includes a ball body and a base layer covering an outer surface of the ball body. After that, the semi-finished product of the golf ball is rotated at a predetermined rotation speed, and a color paint is applied to the semi-finished product of the golf ball in a spraying manner from each of an upper position and a lower position.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: February 7, 2023
    Assignee: FOREMOST GOLF MFG. LTD.
    Inventors: Chia-Sheng Huang, Chi-Ling Lin, Chia-Cheng Wu, Ching-Hsiang Liu
  • Patent number: 11518476
    Abstract: A multi-speed hub gear includes an axle, a planetary gear set, a clutch, a transmission member, a guide wheel, a compressed clutch spring, a shift mechanism and a torsional spring. While in switching a low gear to a high gear, the shift mechanism transforms a rotational motion into a linear motion for twisting the torsional spring. The compressed clutch spring pushes the clutch to displace from the transmission member toward the planetary gear set. While in switching the high gear to the low gear, the torsional spring drives the shift mechanism to transform the rotational motion into the linear motion, such that the clutch can displace from the planetary gear set toward the transmission member, and compress the compressed clutch spring.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: December 6, 2022
    Assignee: SUN RACE STURMEY-ARCHER INC.
    Inventors: Hsing-Yang Su, Chia-Sheng Huang
  • Publication number: 20220266293
    Abstract: A method for manufacturing a golf ball having a multi-layered pattern is provided. Firstly, a semi-finished product of the golf ball is provided and includes a ball-shaped body and a base layer covering an outer surface of the ball-shaped body. Then, the semi-finished product of the golf ball is rotated at a predetermined rotation speed, and a color paint is applied to the semi-finished product of the golf ball by spraying from each of an upper position, a middle position, and a lower position. The multi-layered pattern includes an upper-layer pattern area, a mid-layer pattern area, and a lower-layer pattern area that are different in color from each other.
    Type: Application
    Filed: October 26, 2021
    Publication date: August 25, 2022
    Inventors: CHIA-SHENG HUANG, CHI-LING LIN, CHIA-CHENG WU, CHING-HSIANG LIU
  • Patent number: 11389702
    Abstract: An apparatus and method of indicating the ball center of gravity position. The method of indicating the ball center of gravity position includes the following step of: moving the ball to a rotating member of a rotating device; driving the rotating member to rotate the ball along a axis of rotation of the rotating device, and adjust the center of gravity of the ball corresponding to the position of the rotating device; moving the ball onto a first carrier of a first transport device; and marking an identification mark on a predetermined area of the ball.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: July 19, 2022
    Assignees: Dick's Sporting Goods, Inc., Foremost Golf Mfg., Ltd.
    Inventors: Chia-Sheng Huang, Chia-Cheng Wu, Chih-Sheng Tseng