Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.

Abstract: Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of semiconductor layers. The semiconductor layers are stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. A third conductive feature is formed over the first epitaxy region and within the oxide diffusion region. A fourth conductive feature is formed over the second epitaxy region and within the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features.

Abstract: A method (of writing to a ferroelectric field-effect transistor (FeFET) configured as a 2-bit storage device that stores two bits, wherein the FeFET includes a first source/drain (S/D) terminal, a second S/D terminal, a gate terminal and a ferroelectric layer, a second bit being at a first end of the ferroelectric layer, the first end being proximal to the first S/D terminal) includes: setting the second bit to a logical 1 value, the setting a second bit including applying a gate voltage to the gate terminal, and applying a first source/drain voltage to the second S/D terminal; and wherein the first source/drain voltage is lower than the gate voltage.

Abstract: A memory circuit includes a first memory cell on a first layer, a second memory cell on a second layer different from the first layer, a first select transistor on a third layer different from the first layer and the second layer, and a first bit line extending in a first direction, and being coupled to the first memory cell and the second memory cell. The memory circuit further includes a first source line extending in the first direction, being coupled to the first memory cell, the second memory cell and the first select transistor, and being separated from the first bit line in a second direction different from the first direction. memory circuit includes a second source line extending in the first direction, and being coupled to the first select transistor.

Abstract: Systems and methods are provided herein for controlling the speed on each wheel of a vehicle, possibly operating a vehicle in a speed control mode. In response to receiving input to engage speed control mode and receiving an accelerator pedal input, the system determines a target wheel speed based on the accelerator pedal input, monitors wheel speed of each of a plurality of wheels and determines, for each monitored wheel, a difference based on the monitored wheel speed and the target wheel speed. A torque is provided to each of the plurality of wheels based on the respective difference to achieve the target wheel speed.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Abstract: High voltage discharge is provided. A system can include an electric motor of an electric vehicle electrically connected to a capacitor. A switching component can be connected with and intermediary to the electric motor and the capacitor. A controller can cause the switching component to enter a first state to cause the electric motor to convert electrical power of the capacitor to mechanical power to propel the electric vehicle, or convert mechanical power from a drive system of the electric vehicle to electrical power to charge the capacitor. The controller can cause the switching component to enter, in response to detection by the controller of an indication to discharge the capacitor, a second state to isolate the electric motor from the capacitor.

Abstract: A memory device includes a programming transistor and a reading transistor of an anti-fuse memory cell. The programming transistor includes first semiconductor nanostructures vertically spaced apart from one another, each of the first semiconductor nanostructures having a first width along a first lateral direction. The reading transistor includes second semiconductor nanostructures vertically spaced apart from one another, each of the second semiconductor nanostructures having a second width different from the first width along the second direction. The memory device also includes a first and a second gate metals. The first gate metal wraps around each of the first semiconductor nanostructures with a first gate dielectric disposed therein. The second gate metal wraps around each of the second semiconductor nanostructures with a second gate dielectric disposed therein.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

Abstract: A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.

Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.

Abstract: A system may include a first acoustic event detection (AED) component configured to detect a predetermined set of acoustic events, and include a second AED component configured to detect custom acoustic events that a user configures a device to detect. The first and second AED components are configured to perform task-specific processing, and may receive as input the same acoustic feature data corresponding to audio data that potentially represents occurrence of one or more events. Based on processing by the first and second AED components, a device may output data indicating that one or more acoustic events occurred, where the acoustic events may be a predetermined acoustic event and/or a custom acoustic event.

Abstract: A basecoat coating composition includes an aromatic polyurethane pre-polymer having isocyanate terminal end groups, a first solvent and optionally a second VOC-exempt solvent, in which the total composition formulation has a VOC content of less than 97 g/L. A topcoat coating composition includes an aliphatic polyurethane pre-polymer having isocyanate terminal end groups, a first solvent and optionally a second VOC-exempt solvent, in which the total composition formulation has a VOC content of less than or equal to 95 g/L. The total composition formulations of the basecoat and/or topcoat may have a VOC content of less than 50 g/L. A membrane system may include an optional primer coating, and the above described basecoat and topcoat coating compositions.

Abstract: A test structure and methods of forming the same are described. In some embodiments, the structure includes a first portion having a first thickness, and the first portion comprises one or more dielectric layers. The test structure further includes a second portion disposed adjacent the first portion, the second portion has a second thickness substantially less than the first thickness, and the second portion includes the one or more dielectric layers and a first plurality of test conductive features disposed in the one or more dielectric layers. The test structure further includes a third portion disposed adjacent the second portion, the third portion has a third thickness substantially less than the second thickness, and the third portion comprises the one or more dielectric layers and a second plurality of test conductive features disposed in the one or more dielectric layers.

Abstract: A word line driving circuit includes a first circuit and a second circuit. The first circuit is configured to provide a first word line driving voltage and a second word line driving voltage based on a first control signal, a second control signal, a first bias voltage, a second bias voltage and a base voltage. The second circuit is configured to provide the first control signal and the second control signal based on a third control signal, a fourth control signal, a word line control signal, a reverse word line control signal, the first bias voltage, the second bias voltage and the base voltage. The first bias voltage and the second bias voltage have different levels during the read mode and the program mode for adaptively adjusting the read voltage and the program voltage, thereby improving the data access time.

Abstract: A method for tuning an envelope tracking (ET) system includes: determining a setting combination from a plurality of setting available to the ET system, wherein determining the setting combination from the plurality of setting available to the ET system includes: determining, by a processing module, a first setting in a plurality of first settings included in the plurality of settings, and configuring the ET system by the first setting; and after the ET system is configured by the first setting, determining, by the processing module, a second setting in a plurality of second settings included in the plurality of settings, and configuring the ET system by the second setting. In addition, the setting combination includes the first setting and the second setting.

Abstract: A power circuit is adapted for providing a programming voltage to an electronic fuse circuit, and includes a pass transistor of a P-type metal-oxide-semiconductor transistor, a buffer circuit, and a bulk voltage control circuit. The pass transistor includes a bulk electrode, a gate electrode, a first source/drain electrode receiving a system high voltage, and a second source/drain electrode connected to a bit line. The buffer circuit provides a control voltage to the gate electrode of the pass transistor. The pass transistor is turned on during a programming operation and turned off during a reading operation. The bulk voltage control circuit independently provides a bulk voltage to the bulk electrode. A last-stage buffer of the buffer circuit is also activated by the bulk voltage to control the pass transistor during the reading operation of the electronic fuse circuit. A method for providing power to an electronic fuse circuit is also provided.

Abstract: A power circuit is adapted for providing a programming voltage to an electronic fuse circuit, and includes a pass transistor of a P-type metal-oxide-semiconductor transistor, a buffer circuit, and a bulk voltage control circuit. The pass transistor includes a bulk electrode, a gate electrode, a first source/drain electrode receiving a system high voltage, and a second source/drain electrode connected to a bit line. The buffer circuit provides a control voltage to the gate electrode of the pass transistor. The pass transistor is turned on during a programming operation and turned off during a reading operation. The bulk voltage control circuit independently provides a bulk voltage to the bulk electrode. A last-stage buffer of the buffer circuit is also activated by the bulk voltage to control the pass transistor during the reading operation of the electronic fuse circuit. A method for providing power to an electronic fuse circuit is also provided.

Abstract: A word line driving circuit includes a first circuit and a second circuit. The first circuit is configured to provide a first word line driving voltage and a second word line driving voltage based on a first control signal, a second control signal, a first bias voltage, a second bias voltage and a base voltage. The second circuit is configured to provide the first control signal and the second control signal based on a third control signal, a fourth control signal, a word line control signal, a reverse word line control signal, the first bias voltage, the second bias voltage and the base voltage. The first bias voltage and the second bias voltage have different levels during the read mode and the program mode for adaptively adjusting the read voltage and the program voltage, thereby improving the data access time.

Abstract: A light-emitting diode device is provided. First and second green conversion materials are respectively configured to convert a blue light emitted from a blue light-emitting diode to generate a first green light with a first wavelength range and a first wavelength FWHM, and a second green light with a second wavelength range and a second wavelength FWHM. The second wavelength FWHM is smaller than the first wavelength FWHM. A lower bound of the first wavelength range is smaller than a lower bound of the second wavelength range, and an upper bound of the second wavelength range is greater than an upper bound of the first wavelength range. An output light emitted from the light-emitting diode device has a spectral characteristic of less than 50% of TÜV Rheinland and more than 90% of wide color gamut.