Patents by Inventor Chia-Wei Huang
Chia-Wei Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250107117Abstract: A Schottky diode includes a substrate with an epitaxy layer on which a cathode region and an anode region are defined. A cathode structure and an anode structure are formed in the cathode region and the anode region respectively and horizontally separated by a distance. The anode structure includes a plurality of p-type doped regions diffused from the epitaxy layer toward the substrate, with an interval is formed between adjacent two p-type doped regions. A backside metal film and a backside protection layer are sequentially formed on a back surface of the substrate. Since the manufacturing of the Schottky diode does not involve wire bonding and molding processes, the overall thickness of the Schottky diode is reduced and heat dissipation is improved. With the backside metal film on the back side of the substrate, an equivalent resistance and a forward voltage of the Schottky diode can be reduced.Type: ApplicationFiled: November 15, 2023Publication date: March 27, 2025Inventors: CHUNG-HSIUNG HO, CHI-HSUEH LI, CHIA-WEI CHEN, YU-MING HSU, WEN-LIANG HUANG, MING-KUN HSIN, SHIH-MING CHEN
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Publication number: 20250085548Abstract: A light field display module including a light field display layer, an adjustment layer, and an image forming layer is provided. The light field display layer is configured to form a light field image beam. The adjustment layer is disposed on a path of the light field image beam, and configured to adjust the light field image beam. The image forming layer is disposed on the path of the light field image beam from the adjustment layer, and configured to change a position of a light field image by changing a direction of the light field image beam. The image forming layer has multiple optical micro-structures.Type: ApplicationFiled: August 1, 2024Publication date: March 13, 2025Applicant: Industrial Technology Research InstituteInventors: Szu-Wei Wu, Yi-Hsiang Huang, Chia-Ping Lin, Yu-Hsiang Liu, Hung Tsou
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Publication number: 20250085764Abstract: A method of performing power saving control on a display device includes: generating, by a timing controller of the display device, a power saving start indication and a power saving end indication in response to changing of a refresh rate of the display device; receiving, by a source driver of the display device, the power saving start indication and the power saving end indication; in response to the power saving start indication, allowing a part of circuitry of the source driver to be powered down during a vertical blanking interval; and in response to the power saving end indication, allowing the powered down part of circuitry of the source driver to be woken up during the vertical blanking interval.Type: ApplicationFiled: September 7, 2023Publication date: March 13, 2025Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Hung-Yu Huang, Shu-Ming Chang, Chia-Hui Wang, Shiang-Wei Wang, Sheng-Wen Huang, Tsung-Yi Tsai
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Patent number: 12248353Abstract: A method of performing power saving control on a display device includes: generating, by a timing controller of the display device, a power saving start indication and a power saving end indication in response to changing of a refresh rate of the display device; receiving, by a source driver of the display device, the power saving start indication and the power saving end indication; in response to the power saving start indication, allowing a part of circuitry of the source driver to be powered down during a vertical blanking interval; and in response to the power saving end indication, allowing the powered down part of circuitry of the source driver to be woken up during the vertical blanking interval.Type: GrantFiled: September 7, 2023Date of Patent: March 11, 2025Assignee: HIMAX TECHNOLOGIES LIMITEDInventors: Hung-Yu Huang, Shu-Ming Chang, Chia-Hui Wang, Shiang-Wei Wang, Sheng-Wen Huang, Tsung-Yi Tsai
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Publication number: 20250081730Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.Type: ApplicationFiled: June 26, 2024Publication date: March 6, 2025Inventors: Andrew Lin, Alper Ozgurluk, Chao Liang Chien, Cheuk Chi Lo, Chia-Yu Chen, Chien-Chung Wang, Chih Pang Chang, Chih-Hung Yu, Chih-Wei Chang, Chin Wei Hsu, ChinWei Hu, Chun-Kai Tzeng, Chun-Ming Tang, Chun-Yao Huang, Hung-Che Ting, Jung Yen Huang, Lungpao Hsin, Shih Chang Chang, Tien-Pei Chou, Wen Sheng Lo, Yu-Wen Liu, Yung Da Lai
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Publication number: 20250080756Abstract: A method and apparatus for inter prediction in video coding system are disclosed. According to the method, one or more model parameters of one or more cross-color models for the second-color block are determined. Then, cross-color predictors for the second-color block are determined, wherein one cross-color predictor value for the second-color block is generated for each second-color pixel of the second-color block by applying said one or more cross-color models to corresponding reconstructed or predicted first-color pixels. The input data associated with the second-color block is encoded using prediction data comprising the cross-color predictors for the second-color block at the encoder side, or the input data associated with the second-color block is decoded using the prediction data comprising the cross-color predictors for the second-color block at the decoder side.Type: ApplicationFiled: December 20, 2022Publication date: March 6, 2025Inventors: Man-Shu CHIANG, Olena CHUBACH, Yu-Ling HSIAO, Chia-Ming TSAI, Chun-Chia CHEN, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
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Patent number: 12243872Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first channel region disposed over a substrate, a second channel region disposed adjacent the first channel region, a gate electrode layer disposed in the first and second channel regions, and a first dielectric feature disposed adjacent the gate electrode layer. The first dielectric feature includes a first dielectric material having a first thickness. The structure further includes a second dielectric feature disposed between the first and second channel regions, and the second dielectric feature includes a second dielectric material having a second thickness substantially less than the first thickness. The second thickness ranges from about 1 nm to about 20 nm.Type: GrantFiled: February 15, 2022Date of Patent: March 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Huang Huang, Yu-Ling Cheng, Shun-Hui Yang, An Chyi Wei, Chia-Jen Chen, Shang-Shuo Huang, Chia-I Lin, Chih-Chang Hung
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Publication number: 20250066793Abstract: Disclosed herein are novel single-stranded anti-sense oligonucleotides (ASOs) capable of reducing the transcription of thioredoxin domain containing protein 5 (TXNDC5) mRNA. Also disclosed is use of the single-stranded ASOs as disclosed herein for manufacturing medicaments suitable for treating a disease associated with upregulation of TXNDC5. Accordingly, a pharmaceutical composition comprising the disclosed ASO molecules is provided; as well as a method of treating a subject suffering from TXNDC5-mediated disease via administering to the subject the disclosed single-stranded ASO molecules.Type: ApplicationFiled: December 28, 2022Publication date: February 27, 2025Inventors: Ying-Shuan LAILEE, Chia-Wei LIU, Chi-Tang WANG, Pei-Yi TSAI, Chung-Hsiun WU, King LAM, Wei-Ting SUN, Kai-Chien YANG, Hung-Jyun HUANG
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Publication number: 20250072108Abstract: Capacitor cells are provided. A first PMOS transistor has a source connected to a power supply and a drain connected to a first node. A first NMOS transistor has a source connected to a ground and a drain connected to a second node. A second PMOS transistor has a source connected to the second node and a drain connected to the first node. A second NMOS transistor has a source connected to the ground and a drain connected to the first node. A first P+ doped region is shared by drains of the first and second PMOS transistors. A first gate metal is between the first P+ doped region and a second P+ doped region. A first N+ doped region is shared by sources of the first and second NMOS transistors. A second gate metal is between the first N+ doped region and a second N+ doped region.Type: ApplicationFiled: November 12, 2024Publication date: February 27, 2025Inventors: Chien-Yao HUANG, Wun-Jie LIN, Chia-Wei HSU, Yu-Ti SU
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Patent number: 12237398Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.Type: GrantFiled: June 4, 2021Date of Patent: February 25, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Ming Kuo, Po-Jen Chuang, Yu-Ren Wang, Ying-Wei Yen, Fu-Jung Chuang, Ya-Yin Hsiao, Nan-Yuan Huang
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Patent number: 12237350Abstract: An NMOS structure includes a semiconductor substrate, a dielectric structure, a source doped region, a drain doped region, a channel region, a gate structure and two isolation P-type wells. The dielectric structure is formed in the semiconductor substrate to define an active region, in which the source/drain doped region and the channel region are formed. The channel region includes two opposite first sides and two opposite second sides. The source/drain doped region is respectively formed between the two second sides and the dielectric structure. The gate structure is formed on the semiconductor substrate. The gate structure covers a part of the dielectric structure beside the first sides. The two isolation P-type wells are formed in a part of the dielectric structure not covered by the gate structure. The isolation P-type wells respectively surround a periphery of the source/drain doped region and end at the respective second side.Type: GrantFiled: December 1, 2021Date of Patent: February 25, 2025Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Hau-Yuan Huang, Chia-Chen Tsai, Jia-Bin Yeh, Shou-Wei Hsieh
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Publication number: 20250063155Abstract: A method and apparatus for inter prediction in video coding system are disclosed. According to the method, input data associated with a current block comprising at least one colour block are received. A blending predictor is determined according to a weighted sum of at least two candidate predictions generated based on one or more first hypotheses of prediction, one or more second hypotheses of prediction, or both. The first hypotheses of prediction are generated based on one or more intra prediction modes comprising a DC mode, a planar mode or at least one angular modes. The second hypotheses of prediction are generated based on one or more cross-component modes and a collocated block of said at least one colour block. The input data associated with the colour block is encoded or decoded using the blending predictor.Type: ApplicationFiled: December 20, 2022Publication date: February 20, 2025Inventors: Man-Shu CHIANG, Olena CHUBACH, Chia-Ming TSAI, Yu-Ling HSIAO, Chun-Chia CHEN, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
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Publication number: 20250039356Abstract: A video coding system that uses multiple models to predict chroma samples is provided. The video coding system receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. The video coding system derives multiple prediction linear models based on luma and chroma samples neighboring the current block. The video coding system constructs a composite linear model based on the multiple prediction linear models. The video coding system applies the composite linear model to incoming or reconstructed luma samples of the current block to generate a chroma predictor of the current block. The video coding system uses the chroma predictor to reconstruct chroma samples of the current block or to encode the current block.Type: ApplicationFiled: December 29, 2022Publication date: January 30, 2025Inventors: Chia-Ming TSAI, Chun-Chia CHEN, Yu-Ling HSIAO, Man-Shu CHIANG, Chih-Wei HSU, Olena CHUBACH, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
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Patent number: 12207449Abstract: A cooling apparatus is provided. An external cooling fluid flows into an external inlet opening from an external inlet pipe and passes through a heat exchanger to flow out of an external outlet opening to an external outlet pipe. An internal cooling fluid flows into an internal inlet pipe from the server and flows into an internal inlet opening from the internal inlet pipe and passes through the heat exchanger for heat exchange with the external cooling fluid to flow out of an internal outlet opening to an internal outlet pipe. A hot-swap pump has a pump main body, an inlet anti-leakage pipe, an outlet anti-leakage pipe and a hot-swap connector. The inlet anti-leakage pipe includes an inlet connector and an inlet anti-leakage valve. The outlet anti-leakage pipe includes an outlet connector and an outlet anti-leakage valve. The hot-swap connector is electrically connected to the pump main body.Type: GrantFiled: April 5, 2022Date of Patent: January 21, 2025Assignee: Super Micro Computer, Inc.Inventors: Chia-Wei Chen, Te-Chang Lin, Yueh-Ming Liu, Yu-Hsiang Huang, Ya-Lin Liu, Chi-Che Chang
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Patent number: 12204163Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: February 5, 2024Date of Patent: January 21, 2025Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Publication number: 20250024383Abstract: This disclosure provides systems, methods, and devices for wireless communication that support transmission of power limit indications for a UE associated with different frequency bands. In a first aspect, a method of wireless communication includes detecting a first trigger condition for transmission of at least a first indication of a first transmission power limit of the UE and a second indication of a second transmission power limit of the UE, wherein the first transmission power limit is associated with a first frequency band supported by the UE and the second transmission power limit is associated with a second frequency band supported by the UE and transmitting, to a first network node associated with the first frequency band, the first indication and the second indication in accordance with detection of the first trigger condition. Other aspects and features are also claimed and described.Type: ApplicationFiled: July 11, 2023Publication date: January 16, 2025Inventors: Chan-Jui Chian, Chia-Wei Chang, Tzui Lu, Tsung-Te Hou, Kai-Chun Huang, Wei-Che Chang, Yuwei Pan, Cheng-Ting Tsai
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Publication number: 20240288489Abstract: The present disclosure provides a wafer. The wafer includes a die, a scribe line adjacent to the die, and a test circuit adjacent to the scribe line. The test circuit includes a first switch configured to simultaneously couple a first DUT of a first set of DUTs arranged in a first column and a second DUT of a second set of DUTs arranged in a second column to a signal supply node. The test circuit includes a second switch configured to simultaneously couple the first DUT and the second DUT to a signal receive node. The second switch has a node directly coupled to the first DUT, the second DUT, and the first switch. There is no switch connected between the first DUT and the second DUT.Type: ApplicationFiled: May 6, 2024Publication date: August 29, 2024Inventors: CHIA-WEI HUANG, WEI-JHIH WANG, CHENG-CHENG KUO, YUAN-YAO CHANG
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Patent number: 12007431Abstract: The present disclosure provides a wafer. The wafer includes a die, a scribe line adjacent to the die, and a test circuit adjacent to the scribe line. The test circuit includes a first switch, a second switch, and a third switch. The first switch has a first node coupled to a first device-under-test and a second node coupled to a first signal supply node. The second switch has a first node coupled to the second DUT and a second node coupled to the first signal supply node. The third switch has a first node directly coupled to the first DUT and the second DUT. The third switch has a second node coupled to a second signal supply node. The third switch selectively couples both of the first DUT and the second DUT to the second signal supply node.Type: GrantFiled: August 27, 2021Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chia-Wei Huang, Wei-Jhih Wang, Cheng-Cheng Kuo, Yuan-Yao Chang
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Publication number: 20240162038Abstract: A photomask structure including a first layout pattern and a second layout pattern is provided. The second layout pattern is located on one side of the first layout pattern. The first layout pattern and the second layout pattern are separated from each other. The first layout pattern has a first edge and a second edge opposite to each other. The second layout pattern has a third edge and a fourth edge opposite to each other. The third edge of the second layout pattern is adjacent to the first edge of the first layout pattern. The second layout pattern includes a first extension portion exceeding an end of the first layout pattern. The first extension portion includes a first protruding portion protruding from the third edge of the second layout pattern. The first protruding portion exceeds the first edge of the first layout pattern.Type: ApplicationFiled: February 10, 2023Publication date: May 16, 2024Applicant: United Microelectronics Corp.Inventors: Chien Heng Liu, Chia-Wei Huang, Yung-Feng Cheng, Ming-Jui Chen
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Patent number: D1063950Type: GrantFiled: May 24, 2021Date of Patent: February 25, 2025Assignee: VIVOTEK INC.Inventors: Kuan-Hung Chen, Kai-Sheng Chuang, Chia-Chi Chang, Yu-Fang Huang, Kai-Ting Yu, Wen-Chun Chen, Shu-Jung Hsu, Tsao-Wei Hung