Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, and a barrier layer. The first conductive feature is disposed on the first dielectric layer, the second dielectric layer is disposed on the first dielectric layer and surrounds the sidewalls of the first conductive feature, the barrier layer is disposed between the first dielectric layer and the second dielectric layer and between the sidewalls of the first conductive feature and the second dielectric layer.

Abstract: The semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first dielectric layer, a first metal layer, a second metal layer, a first etching stop layer, a second etching stop layer, a second dielectric layer, a first via and a second via. The first metal layer and the second metal are embedded in the first dielectric layer. The first etching stop layer is disposed on the first dielectric layer. The second etching stop layer is disposed on the first etching stop layer. The second dielectric layer is disposed on the second etching stop layer. The first via and the second via are embedded in the second dielectric layer. A width of the second etching stop layer is smaller a width of the first etching stop layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first low dielectric constant (low-k) layer, a first metal layer, a metal cap layer, a dielectric on dielectric (DoD) layer, an etch stop layer (ESL), a second low-k layer, a metal via and a second metal layer. The dielectric constant of the first low-k layer is less than 4. The first metal layer is embodied in the first low-k layer. The first low-k layer exposes the first metal layer. The metal cap layer is disposed on the first metal layer. The DoD layer is disposed on the first low-k layer. The etch stop layer is disposed on the metal cap layer and the DoD layer. The second low-k layer is disposed above the etch stop layer. The metal via is embodied in the second low-k layer and connected to the first metal layer.

Abstract: The present disclosure is at least directed to utilizing air curtain devices to form air curtains to separate and isolate areas in which respective workpieces are stored from a transfer compartment within a workpiece processing apparatus. The transfer compartment of the workpiece processing apparatus includes a robot configured to transfer or transport ones of the workpieces to and from these respective storage areas through the transfer compartment and to and from a tool compartment. A tool is present in the tool compartment for processing and refining the respective workpieces. Clean dry air (CDA) may be circulated through the respective storage areas. The air curtains formed by the air curtain devices and the circulation of CDA through the respective storage areas reduces the likelihood of the generation of defects, damages, and degradation of the workpieces when present within the workpiece processing apparatus.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A Schottky diode includes a substrate with an epitaxy layer on which a cathode region and an anode region are defined. A cathode structure and an anode structure are formed in the cathode region and the anode region respectively and horizontally separated by a distance. The anode structure includes a plurality of p-type doped regions diffused from the epitaxy layer toward the substrate, with an interval is formed between adjacent two p-type doped regions. A backside metal film and a backside protection layer are sequentially formed on a back surface of the substrate. Since the manufacturing of the Schottky diode does not involve wire bonding and molding processes, the overall thickness of the Schottky diode is reduced and heat dissipation is improved. With the backside metal film on the back side of the substrate, an equivalent resistance and a forward voltage of the Schottky diode can be reduced.

Abstract: A method of performing power saving control on a display device includes: generating, by a timing controller of the display device, a power saving start indication and a power saving end indication in response to changing of a refresh rate of the display device; receiving, by a source driver of the display device, the power saving start indication and the power saving end indication; in response to the power saving start indication, allowing a part of circuitry of the source driver to be powered down during a vertical blanking interval; and in response to the power saving end indication, allowing the powered down part of circuitry of the source driver to be woken up during the vertical blanking interval.

Abstract: A light field display module including a light field display layer, an adjustment layer, and an image forming layer is provided. The light field display layer is configured to form a light field image beam. The adjustment layer is disposed on a path of the light field image beam, and configured to adjust the light field image beam. The image forming layer is disposed on the path of the light field image beam from the adjustment layer, and configured to change a position of a light field image by changing a direction of the light field image beam. The image forming layer has multiple optical micro-structures.

Abstract: A method of performing power saving control on a display device includes: generating, by a timing controller of the display device, a power saving start indication and a power saving end indication in response to changing of a refresh rate of the display device; receiving, by a source driver of the display device, the power saving start indication and the power saving end indication; in response to the power saving start indication, allowing a part of circuitry of the source driver to be powered down during a vertical blanking interval; and in response to the power saving end indication, allowing the powered down part of circuitry of the source driver to be woken up during the vertical blanking interval.

Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: A method and apparatus for inter prediction in video coding system are disclosed. According to the method, one or more model parameters of one or more cross-color models for the second-color block are determined. Then, cross-color predictors for the second-color block are determined, wherein one cross-color predictor value for the second-color block is generated for each second-color pixel of the second-color block by applying said one or more cross-color models to corresponding reconstructed or predicted first-color pixels. The input data associated with the second-color block is encoded using prediction data comprising the cross-color predictors for the second-color block at the encoder side, or the input data associated with the second-color block is decoded using the prediction data comprising the cross-color predictors for the second-color block at the decoder side.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first channel region disposed over a substrate, a second channel region disposed adjacent the first channel region, a gate electrode layer disposed in the first and second channel regions, and a first dielectric feature disposed adjacent the gate electrode layer. The first dielectric feature includes a first dielectric material having a first thickness. The structure further includes a second dielectric feature disposed between the first and second channel regions, and the second dielectric feature includes a second dielectric material having a second thickness substantially less than the first thickness. The second thickness ranges from about 1 nm to about 20 nm.

Abstract: Capacitor cells are provided. A first PMOS transistor has a source connected to a power supply and a drain connected to a first node. A first NMOS transistor has a source connected to a ground and a drain connected to a second node. A second PMOS transistor has a source connected to the second node and a drain connected to the first node. A second NMOS transistor has a source connected to the ground and a drain connected to the first node. A first P+ doped region is shared by drains of the first and second PMOS transistors. A first gate metal is between the first P+ doped region and a second P+ doped region. A first N+ doped region is shared by sources of the first and second NMOS transistors. A second gate metal is between the first N+ doped region and a second N+ doped region.

Abstract: Disclosed herein are novel single-stranded anti-sense oligonucleotides (ASOs) capable of reducing the transcription of thioredoxin domain containing protein 5 (TXNDC5) mRNA. Also disclosed is use of the single-stranded ASOs as disclosed herein for manufacturing medicaments suitable for treating a disease associated with upregulation of TXNDC5. Accordingly, a pharmaceutical composition comprising the disclosed ASO molecules is provided; as well as a method of treating a subject suffering from TXNDC5-mediated disease via administering to the subject the disclosed single-stranded ASO molecules.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.

Abstract: An NMOS structure includes a semiconductor substrate, a dielectric structure, a source doped region, a drain doped region, a channel region, a gate structure and two isolation P-type wells. The dielectric structure is formed in the semiconductor substrate to define an active region, in which the source/drain doped region and the channel region are formed. The channel region includes two opposite first sides and two opposite second sides. The source/drain doped region is respectively formed between the two second sides and the dielectric structure. The gate structure is formed on the semiconductor substrate. The gate structure covers a part of the dielectric structure beside the first sides. The two isolation P-type wells are formed in a part of the dielectric structure not covered by the gate structure. The isolation P-type wells respectively surround a periphery of the source/drain doped region and end at the respective second side.

Abstract: A method and apparatus for inter prediction in video coding system are disclosed. According to the method, input data associated with a current block comprising at least one colour block are received. A blending predictor is determined according to a weighted sum of at least two candidate predictions generated based on one or more first hypotheses of prediction, one or more second hypotheses of prediction, or both. The first hypotheses of prediction are generated based on one or more intra prediction modes comprising a DC mode, a planar mode or at least one angular modes. The second hypotheses of prediction are generated based on one or more cross-component modes and a collocated block of said at least one colour block. The input data associated with the colour block is encoded or decoded using the blending predictor.

Abstract: A video coding system that uses multiple models to predict chroma samples is provided. The video coding system receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. The video coding system derives multiple prediction linear models based on luma and chroma samples neighboring the current block. The video coding system constructs a composite linear model based on the multiple prediction linear models. The video coding system applies the composite linear model to incoming or reconstructed luma samples of the current block to generate a chroma predictor of the current block. The video coding system uses the chroma predictor to reconstruct chroma samples of the current block or to encode the current block.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.