Patents by Inventor Chia-Wei Huang
Chia-Wei Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250066793Abstract: Disclosed herein are novel single-stranded anti-sense oligonucleotides (ASOs) capable of reducing the transcription of thioredoxin domain containing protein 5 (TXNDC5) mRNA. Also disclosed is use of the single-stranded ASOs as disclosed herein for manufacturing medicaments suitable for treating a disease associated with upregulation of TXNDC5. Accordingly, a pharmaceutical composition comprising the disclosed ASO molecules is provided; as well as a method of treating a subject suffering from TXNDC5-mediated disease via administering to the subject the disclosed single-stranded ASO molecules.Type: ApplicationFiled: December 28, 2022Publication date: February 27, 2025Inventors: Ying-Shuan LAILEE, Chia-Wei LIU, Chi-Tang WANG, Pei-Yi TSAI, Chung-Hsiun WU, King LAM, Wei-Ting SUN, Kai-Chien YANG, Hung-Jyun HUANG
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Publication number: 20250072108Abstract: Capacitor cells are provided. A first PMOS transistor has a source connected to a power supply and a drain connected to a first node. A first NMOS transistor has a source connected to a ground and a drain connected to a second node. A second PMOS transistor has a source connected to the second node and a drain connected to the first node. A second NMOS transistor has a source connected to the ground and a drain connected to the first node. A first P+ doped region is shared by drains of the first and second PMOS transistors. A first gate metal is between the first P+ doped region and a second P+ doped region. A first N+ doped region is shared by sources of the first and second NMOS transistors. A second gate metal is between the first N+ doped region and a second N+ doped region.Type: ApplicationFiled: November 12, 2024Publication date: February 27, 2025Inventors: Chien-Yao HUANG, Wun-Jie LIN, Chia-Wei HSU, Yu-Ti SU
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Patent number: 12237350Abstract: An NMOS structure includes a semiconductor substrate, a dielectric structure, a source doped region, a drain doped region, a channel region, a gate structure and two isolation P-type wells. The dielectric structure is formed in the semiconductor substrate to define an active region, in which the source/drain doped region and the channel region are formed. The channel region includes two opposite first sides and two opposite second sides. The source/drain doped region is respectively formed between the two second sides and the dielectric structure. The gate structure is formed on the semiconductor substrate. The gate structure covers a part of the dielectric structure beside the first sides. The two isolation P-type wells are formed in a part of the dielectric structure not covered by the gate structure. The isolation P-type wells respectively surround a periphery of the source/drain doped region and end at the respective second side.Type: GrantFiled: December 1, 2021Date of Patent: February 25, 2025Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Hau-Yuan Huang, Chia-Chen Tsai, Jia-Bin Yeh, Shou-Wei Hsieh
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Patent number: 12237398Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.Type: GrantFiled: June 4, 2021Date of Patent: February 25, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Ming Kuo, Po-Jen Chuang, Yu-Ren Wang, Ying-Wei Yen, Fu-Jung Chuang, Ya-Yin Hsiao, Nan-Yuan Huang
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Publication number: 20250063155Abstract: A method and apparatus for inter prediction in video coding system are disclosed. According to the method, input data associated with a current block comprising at least one colour block are received. A blending predictor is determined according to a weighted sum of at least two candidate predictions generated based on one or more first hypotheses of prediction, one or more second hypotheses of prediction, or both. The first hypotheses of prediction are generated based on one or more intra prediction modes comprising a DC mode, a planar mode or at least one angular modes. The second hypotheses of prediction are generated based on one or more cross-component modes and a collocated block of said at least one colour block. The input data associated with the colour block is encoded or decoded using the blending predictor.Type: ApplicationFiled: December 20, 2022Publication date: February 20, 2025Inventors: Man-Shu CHIANG, Olena CHUBACH, Chia-Ming TSAI, Yu-Ling HSIAO, Chun-Chia CHEN, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
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Publication number: 20250039356Abstract: A video coding system that uses multiple models to predict chroma samples is provided. The video coding system receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. The video coding system derives multiple prediction linear models based on luma and chroma samples neighboring the current block. The video coding system constructs a composite linear model based on the multiple prediction linear models. The video coding system applies the composite linear model to incoming or reconstructed luma samples of the current block to generate a chroma predictor of the current block. The video coding system uses the chroma predictor to reconstruct chroma samples of the current block or to encode the current block.Type: ApplicationFiled: December 29, 2022Publication date: January 30, 2025Inventors: Chia-Ming TSAI, Chun-Chia CHEN, Yu-Ling HSIAO, Man-Shu CHIANG, Chih-Wei HSU, Olena CHUBACH, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
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Patent number: 12207449Abstract: A cooling apparatus is provided. An external cooling fluid flows into an external inlet opening from an external inlet pipe and passes through a heat exchanger to flow out of an external outlet opening to an external outlet pipe. An internal cooling fluid flows into an internal inlet pipe from the server and flows into an internal inlet opening from the internal inlet pipe and passes through the heat exchanger for heat exchange with the external cooling fluid to flow out of an internal outlet opening to an internal outlet pipe. A hot-swap pump has a pump main body, an inlet anti-leakage pipe, an outlet anti-leakage pipe and a hot-swap connector. The inlet anti-leakage pipe includes an inlet connector and an inlet anti-leakage valve. The outlet anti-leakage pipe includes an outlet connector and an outlet anti-leakage valve. The hot-swap connector is electrically connected to the pump main body.Type: GrantFiled: April 5, 2022Date of Patent: January 21, 2025Assignee: Super Micro Computer, Inc.Inventors: Chia-Wei Chen, Te-Chang Lin, Yueh-Ming Liu, Yu-Hsiang Huang, Ya-Lin Liu, Chi-Che Chang
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Patent number: 12204163Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: February 5, 2024Date of Patent: January 21, 2025Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Publication number: 20250024383Abstract: This disclosure provides systems, methods, and devices for wireless communication that support transmission of power limit indications for a UE associated with different frequency bands. In a first aspect, a method of wireless communication includes detecting a first trigger condition for transmission of at least a first indication of a first transmission power limit of the UE and a second indication of a second transmission power limit of the UE, wherein the first transmission power limit is associated with a first frequency band supported by the UE and the second transmission power limit is associated with a second frequency band supported by the UE and transmitting, to a first network node associated with the first frequency band, the first indication and the second indication in accordance with detection of the first trigger condition. Other aspects and features are also claimed and described.Type: ApplicationFiled: July 11, 2023Publication date: January 16, 2025Inventors: Chan-Jui Chian, Chia-Wei Chang, Tzui Lu, Tsung-Te Hou, Kai-Chun Huang, Wei-Che Chang, Yuwei Pan, Cheng-Ting Tsai
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Publication number: 20240288489Abstract: The present disclosure provides a wafer. The wafer includes a die, a scribe line adjacent to the die, and a test circuit adjacent to the scribe line. The test circuit includes a first switch configured to simultaneously couple a first DUT of a first set of DUTs arranged in a first column and a second DUT of a second set of DUTs arranged in a second column to a signal supply node. The test circuit includes a second switch configured to simultaneously couple the first DUT and the second DUT to a signal receive node. The second switch has a node directly coupled to the first DUT, the second DUT, and the first switch. There is no switch connected between the first DUT and the second DUT.Type: ApplicationFiled: May 6, 2024Publication date: August 29, 2024Inventors: CHIA-WEI HUANG, WEI-JHIH WANG, CHENG-CHENG KUO, YUAN-YAO CHANG
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Patent number: 12007431Abstract: The present disclosure provides a wafer. The wafer includes a die, a scribe line adjacent to the die, and a test circuit adjacent to the scribe line. The test circuit includes a first switch, a second switch, and a third switch. The first switch has a first node coupled to a first device-under-test and a second node coupled to a first signal supply node. The second switch has a first node coupled to the second DUT and a second node coupled to the first signal supply node. The third switch has a first node directly coupled to the first DUT and the second DUT. The third switch has a second node coupled to a second signal supply node. The third switch selectively couples both of the first DUT and the second DUT to the second signal supply node.Type: GrantFiled: August 27, 2021Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chia-Wei Huang, Wei-Jhih Wang, Cheng-Cheng Kuo, Yuan-Yao Chang
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Publication number: 20240162038Abstract: A photomask structure including a first layout pattern and a second layout pattern is provided. The second layout pattern is located on one side of the first layout pattern. The first layout pattern and the second layout pattern are separated from each other. The first layout pattern has a first edge and a second edge opposite to each other. The second layout pattern has a third edge and a fourth edge opposite to each other. The third edge of the second layout pattern is adjacent to the first edge of the first layout pattern. The second layout pattern includes a first extension portion exceeding an end of the first layout pattern. The first extension portion includes a first protruding portion protruding from the third edge of the second layout pattern. The first protruding portion exceeds the first edge of the first layout pattern.Type: ApplicationFiled: February 10, 2023Publication date: May 16, 2024Applicant: United Microelectronics Corp.Inventors: Chien Heng Liu, Chia-Wei Huang, Yung-Feng Cheng, Ming-Jui Chen
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Publication number: 20230421271Abstract: A transmitter includes a transmitter circuit, a calibration circuit, and a transmitter signal strength indicator circuit. The transmitter circuit is coupled to a power node to receive a supply voltage and transmits an output signal via an antenna. The calibration circuit senses a current of the power node when the transmitter circuit operates in a first frequency band and operates in a second frequency band to generate a signal having different values and generates a calibration signal according to the signals having the different values. The transmitter signal strength indicator circuit detects power of the output signal to generate a first detection signal, and generate a second detection signal according to the calibration signal and the first detection signal. The transmitter circuit adjusts the power of the output signal to be target power according to the second detection signal.Type: ApplicationFiled: June 1, 2023Publication date: December 28, 2023Inventors: CHIA-WEI HUANG, YI-HUA LU
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Patent number: 11839516Abstract: Medical imaging equipment and a medical imaging method are provided. The medical imaging equipment includes medical equipment, a controller, and a head-mounted display. The medical equipment is configured to investigate a body portion and output a first image signal corresponding to the body portion. The first image signal has a first resolution. The controller is coupled to the medical equipment to receive the first image signal and convert the first resolution of the first image signal to a second image signal having a second resolution. The head-mounted display is coupled to the controller to display a display image of the second image signal. The head-mounted display has a direction line. When the head-mounted display faces the body portion, the display image and the body portion are located along to the direction line.Type: GrantFiled: June 8, 2021Date of Patent: December 12, 2023Assignee: Coretronic CorporationInventors: I-Han Chen, Chen Hsiang Shih, Yi-Fa Wang, Chih-Yang Tsai, Chia-Wei Huang
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Publication number: 20230387629Abstract: A connector assembly that may be used to connect an upper circuit board to a lower circuit board is disclosed. The connector assembly includes a base, and a bracket mechanically fastened to the base. The connector assembly also has a handle rotatably coupled to the base. The connector assembly includes a link bar movably coupling the handle to the base. The connector assembly further includes a guiding feature mechanically coupled between the base and the bracket. The guiding feature is configured to direct relative motion between the base and the bracket. The link bar and the guiding feature are also configured to transfer an external force applied to the handle, the external force being transferred to the upper and lower circuit boards via the base and the bracket.Type: ApplicationFiled: August 12, 2022Publication date: November 30, 2023Inventors: Chao-Jung CHEN, Chih-Wei LIN, Chia-Wei HUANG
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Patent number: 11819614Abstract: The present invention discloses a patient interface having an adaptive system, a respiratory mask and a cushion module adapted with the adaptive system. The adaptive system includes a forehead pressure diffusing portion, a cheek buffering portion and a connecting portion. The forehead pressure diffusing portion is disposed in a frame module. The cheek buffering portion is disposed in a cushion module. The connecting portion is positioned between the forehead pressure diffusing portion and the cheek buffering portion. The connecting portion is configured to transmit pressure between the forehead pressure diffusing portion and the cheek buffering portion. Thus, when a user wears a mask or other devices with the adaptive system, a force received by the face of the user could be automatically and appropriately distributed, further improving comfort of the wearer.Type: GrantFiled: June 26, 2019Date of Patent: November 21, 2023Assignee: APEX MEDICAL CORPInventors: Chun-hung Chen, Chih-tsan Chien, Pi-kai Lee, Yu-chen Liu, Chia-wei Huang, Shin-Lan Lin
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Publication number: 20230317778Abstract: A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.Type: ApplicationFiled: June 7, 2023Publication date: October 5, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chien-Heng Liu, Chia-Wei Huang, Hsin-Jen Yu, Yung-Feng Cheng, Ming-Jui Chen
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Publication number: 20230317779Abstract: A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.Type: ApplicationFiled: June 7, 2023Publication date: October 5, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chien-Heng Liu, Chia-Wei Huang, Hsin-Jen Yu, Yung-Feng Cheng, Ming-Jui Chen
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Patent number: 11754614Abstract: The present disclosure provides a method of analyzing a semiconductor device. The method includes providing a first transistor, a second transistor disposed adjacent to the first transistor, and a gate electrode common to the first transistor and the second transistor; connecting a power-supply voltage (Vdd) to the gate electrode to turn on the first transistor, determining a first threshold voltage (Vth) based on the power-supply voltage; switching the power-supply voltage to a ground voltage (Vss); connecting the ground voltage to the gate electrode to turn on the second transistor; and determining a second threshold voltage based on the ground voltage.Type: GrantFiled: April 30, 2021Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wei-Jhih Wang, Chia Wei Huang, Chia-Chia Kan, Yuan-Yao Chang
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Patent number: D1063950Type: GrantFiled: May 24, 2021Date of Patent: February 25, 2025Assignee: VIVOTEK INC.Inventors: Kuan-Hung Chen, Kai-Sheng Chuang, Chia-Chi Chang, Yu-Fang Huang, Kai-Ting Yu, Wen-Chun Chen, Shu-Jung Hsu, Tsao-Wei Hung