Patents by Inventor Chia-Wei Huang

Chia-Wei Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10785158
    Abstract: A system and method provisions IPv4 and IPv6 Internet service and load balancer service. An Internet service and load balancer service provisioning module provisions or activates IPv4 or IPv6 Internet service and load balancer service of a VPC environment. A service chain provisioning management unit manages a lifecycle of activating or terminating of the Internet service and load balancer service, and records orders and provisioning processes of a plurality of service nodes. A network resource enablement and setting unit communicates with the service nodes to activate and set each of the service nodes. A network resource management and allocating unit establishes IP resource pools based on different usages of an IPv4 subnet and an IPv6 subnet, and selects the IP resource pools based on usages to obtain a usable IP address. An IPv4 and IPv6 subnets IP resource pools management module manages the IP resource pools.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: September 22, 2020
    Assignee: CHUNGHWA TELECOM CO., LTD.
    Inventors: Chen-Hsiang Chen, Chia-Wei Huang, Wei-Te Wu, Yao-Te Huang
  • Patent number: 10605855
    Abstract: A method, a test line and a system for detecting defects on a semiconductor wafer are presented. The method includes measuring a current-voltage (IV) curve of a plurality of metal oxide semiconductor (MOS) transistors which are connected in series in a test key; comparing the measured IV curve with a reference curve to obtain a first drain current drop in a linear region and a second drain current drop in a saturation region; and determining whether at least one of the MOS transistor among the MOS transistors of the test key is defected according to at least one of the first drain current drop and the second drain current drop.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: March 31, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Sen Wang, Yuan-Yao Chang, Hung-Chi Chiu, Chia-Wei Huang
  • Publication number: 20200086071
    Abstract: Herein disclosed is a respiratory mask comprising a nose cushion assembly. The nose cushion assembly comprises a base body and a buffering piece. The base body is defined as having a base intake portion and a base connection portion. The base body comprises an air routing piece disposed at the inside of the base body and having a partitioning wall and a wall connection piece. The inside of the partitioning wall encloses an air intake zone. The wall connection piece is disposed outside the partitioning wall and connects with the base intake portion. Between the partitioning wall and the base intake portion there is defined an air outtake zone. The air intake zone is approximately at the center of the base intake portion. The buffering piece connects with the base connection portion and encloses a nose containing room, which in turn connects with the inside of the base body.
    Type: Application
    Filed: September 9, 2019
    Publication date: March 19, 2020
    Inventors: Shu-Chi LIN, Chih-Tsan CHIEN, Chun-Hung CHEN, Sheng-Wei LIN, Pi-Kai LEE, Yu-Chen LIU, Chia-Wei HUANG
  • Publication number: 20200001034
    Abstract: The present invention discloses a patient interface having an adaptive system, a respiratory mask and a cushion module adapted with the adaptive system. The adaptive system includes a forehead pressure diffusing portion, a cheek buffering portion and a connecting portion. The forehead pressure diffusing portion is disposed in a frame module. The cheek buffering portion is disposed in a cushion module. The connecting portion is positioned between the forehead pressure diffusing portion and the cheek buffering portion. The connecting portion is configured to transmit pressure between the forehead pressure diffusing portion and the cheek buffering portion. Thus, when a user wears a mask or other devices with the adaptive system, a force received by the face of the user could be automatically and appropriately distributed, further improving comfort of the wearer.
    Type: Application
    Filed: June 26, 2019
    Publication date: January 2, 2020
    Inventors: Chun-hung Chen, Chih-tsan Chien, Pi-kai Lee, Yu-chen Liu, Chia-wei Huang, Shin-Lan Lin
  • Patent number: 10487922
    Abstract: A method and apparatus are described for moving a tray within a confined space while the tray is bounded by a chassis. The movement of the tray is effected by a driven gear moving along a rack. A driving gear for rotating the driven gear is mounted on a handle or integral with a rotatable handle. The handle is rotatable about a pivot mounted on the chassis to provide the driving force to move the driven gear along the rack.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: November 26, 2019
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chao-Jung Chen, Chih-Hsiang Lee, Chih-Wei Lin, Chia-Wei Huang
  • Patent number: 10444622
    Abstract: A method for generating masks for manufacturing of a semiconductor structure includes the following steps. First, a design pattern is provided to a processor. The design pattern includes at least one first pattern and at least two second patterns shorter than the first pattern, wherein two of the second patterns are arranged in a line along an extending direction of the patterns. Then, the second patterns are elongated by the processor such that the two second patterns arranged in the line are separated from each other by a distance equal to a minimum space of the design pattern. The design pattern is divided into a first set of patterns and a second set of patterns by the processor. A first mask is generated by the processor based on the first set of patterns. A second mask is generated by the processor based on the second set of patterns.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Yeh Wu, Chia-Wei Huang, Yung-Feng Cheng
  • Patent number: 10446663
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a patterned metal gate layer. The substrate includes a first fin segment and a second fin segment respectively protruding from a top surface of the substrate. The first fin segment and the second fin segment respectively extend along a first direction and are arranged along a second direction, the first fin segment comprises a first fin structure at an end of the first fin segment, and the second fin segment comprises a first recess at an end of the second fin segment, and the first recess and the first fin structure are arranged along the second direction. The patterned metal gate layer is disposed on the substrate, and the patterned metal gate layer covers the first fin structure.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tan-Ya Yin, Chia-Wei Huang
  • Patent number: 10424894
    Abstract: A passively Q-switched fiber laser system comprises a pump source and an ring cavity connected with each other. The ring cavity comprises a gain fiber, a directional coupler and a saturable absorber connected in order. The saturable absorber is a quantum-dot polymer composite film, which is fabricated by a simple method comprising steps of: mixing a quantum dot material of lead sulfide (PbS) with a colloidal polymer to form a mixture; and drying the mixture at two different temperatures in two stages respectively. The saturable absorber of the present invention has lower saturating intensity and a plurality of absorption bands comprising 1000 nm to 1100 nm and 1500 nm to 1600 nm. The maximum output power and the maximum pulse energy of the passively Q-switched fiber laser system can be superior to those laser systems using the quantum-dot (QD) polymer composite film as saturable absorber.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: September 24, 2019
    Assignee: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY
    Inventors: Chien-Ming Chen, Yin-Wen Lee, Chia-Wei Huang, Shih-Ken Chen, Jhang-Rong Jiang
  • Patent number: 10387602
    Abstract: A method for generating masks for manufacturing of a semiconductor structure comprises the following steps. A design pattern for features to be formed on a substrate is divided into a first set of patterns and a second set of patterns. The first set of patterns comprises a first pattern corresponding to a first feature, the second set of patterns comprises two second patterns corresponding to two second features, and the first feature will be arranged between the two second features when the features are formed on a substrate. Two assist feature patterns are added into the first set of patterns. The two assist feature patterns are arranged in locations corresponding to the two second features, respectively. A first mask is generated based on the first set of patterns with the assist feature patterns. A second mask is generated based on the second set of patterns.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: August 20, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Yeh Wu, Chia-Wei Huang, Yung-Feng Cheng
  • Publication number: 20190250503
    Abstract: A method for generating masks for manufacturing of a semiconductor structure includes the following steps. First, a design pattern is provided to a processor. The design pattern includes at least one first pattern and at least two second patterns shorter than the first pattern, wherein two of the second patterns are arranged in a line along an extending direction of the patterns. Then, the second patterns are elongated by the processor such that the two second patterns arranged in the line are separated from each other by a distance equal to a minimum space of the design pattern. The design pattern is divided into a first set of patterns and a second set of patterns by the processor. A first mask is generated by the processor based on the first set of patterns. A second mask is generated by the processor based on the second set of patterns.
    Type: Application
    Filed: February 9, 2018
    Publication date: August 15, 2019
    Inventors: Tsung-Yeh WU, Chia-Wei HUANG, Yung-Feng CHENG
  • Patent number: 10375029
    Abstract: A multimedia broadcasting system having a multiple-node structure includes nodes. Each node is coupled to at least one of the nodes, and the nodes include server nodes and multimedia-playing terminal nodes. Each server node is coupled to at least one of the server nodes and provides at least one multimedia content. Each multimedia-playing terminal node receives multimedia content transmitted by a server node of the server nodes and plays the multimedia content. A first server node of the server nodes is coupled to a second server node of the server nodes, and the first server node transmits, via the second server node, a first multimedia content to at least one multimedia-playing terminal node controlled by the second server node. Each multimedia-playing terminal node is a multimedia play terminal including at least one display device or audio playing device.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: August 6, 2019
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Jia-Shiang Chen, Chia-Wei Huang, Shiang Steve Charng, Chia-Sheng Kuo, Cheng-Tao Tan, Heng-Ho Wu
  • Publication number: 20190228127
    Abstract: A method for generating masks for manufacturing of a semiconductor structure comprises the following steps. A design pattern for features to be formed on a substrate is divided into a first set of patterns and a second set of patterns. The first set of patterns comprises a first pattern corresponding to a first feature, the second set of patterns comprises two second patterns corresponding to two second features, and the first feature will be arranged between the two second features when the features are formed on a substrate. Two assist feature patterns are added into the first set of patterns. The two assist feature patterns are arranged in locations corresponding to the two second features, respectively. A first mask is generated based on the first set of patterns with the assist feature patterns. A second mask is generated based on the second set of patterns.
    Type: Application
    Filed: January 25, 2018
    Publication date: July 25, 2019
    Inventors: Tsung-Yeh WU, Chia-Wei HUANG, Yung-Feng CHENG
  • Publication number: 20190186603
    Abstract: A method and apparatus are described for moving a tray within a confined space while the tray is bounded by a chassis. The movement of the tray is effected by a driven gear moving along a rack. A driving gear for rotating the driven gear is mounted on a handle or integral with a rotatable handle. The handle is rotatable about a pivot mounted on the chassis to provide the driving force to move the driven gear along the rack.
    Type: Application
    Filed: March 12, 2018
    Publication date: June 20, 2019
    Inventors: Chao-Jung CHEN, Chih-Hsiang LEE, Chih-Wei LIN, Chia-Wei HUANG
  • Publication number: 20190064250
    Abstract: A method, a test line and a system for detecting defects on a semiconductor wafer are presented. The method includes measuring a current-voltage (IV) curve of a plurality of metal oxide semiconductor (MOS) transistors which are connected in series in a test key; comparing the measured IV curve with a reference curve to obtain a first drain current drop in a linear region and a second drain current drop in a saturation region; and determining whether at least one of the MOS transistor among the MOS transistors of the test key is defected according to at least one of the first drain current drop and the second drain current drop.
    Type: Application
    Filed: August 29, 2017
    Publication date: February 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Sen Wang, Yuan-Yao Chang, Hung-Chi Chiu, Chia-Wei Huang
  • Publication number: 20190013394
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a patterned metal gate layer. The substrate includes a first fin segment and a second fin segment respectively protruding from a top surface of the substrate. The first fin segment and the second fin segment respectively extend along a first direction and are arranged along a second direction, the first fin segment comprises a first fin structure at an end of the first segment, and the second fin segment comprises a first recess at an end of the second fin segment, and the first recess and the first fin structure are arranged along the second direction. The patterned metal gate layer is disposed on the substrate, and the patterned metal gate layer covers the first fin structure.
    Type: Application
    Filed: September 4, 2018
    Publication date: January 10, 2019
    Inventors: Tan-Ya Yin, Chia-Wei Huang
  • Patent number: 10153034
    Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: December 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tan-Ya Yin, Ming-Jui Chen, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang
  • Patent number: 10139723
    Abstract: A method of forming a photomask is provided. A first layout pattern is first provided to a computer system and followed by generating an assist feature pattern by the computer system based on the first layout pattern and adding the assist feature pattern into the first layout pattern to form a second layout pattern. Thereafter, an optical proximity correction process is performed with reference to both the first layout pattern and the assist feature pattern to the second layout pattern without altering the assist feature pattern to form a third layout pattern by the computer system. Then, the third layout pattern is output to form a photomask.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: November 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-I Wei, Chia-Wei Huang, Yung-Feng Cheng
  • Patent number: D857062
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: August 20, 2019
    Assignee: APEX MEDICAL CORP.
    Inventors: Pi-Kai Lee, Yu-Chen Liu, Pei-Ming Chien, Chia-Wei Huang
  • Patent number: D858583
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: September 3, 2019
    Assignee: APEX MEDICAL CORP.
    Inventors: Pi-Kai Lee, Chia-Wei Huang
  • Patent number: D907047
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: January 5, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Hsing-Yi Kao, Ming-Chung Liu, Chia-Wei Huang, Yu-Hsin Chen, Hong-Tien Wang