Abstract: An antenna system includes a dielectric substrate, a ground plane, and a first antenna array. The ground plane is disposed on a second surface of the dielectric substrate. The first antenna array is disposed on a first surface of the dielectric substrate. The first antenna array includes a first transmission line, a first antenna element, a second antenna element, a third antenna element, a fourth antenna element, a fifth antenna element, and a sixth antenna element. The first transmission line has a first feeding point and is coupled to the first antenna element, the second antenna element, the third antenna element, the fourth antenna element, the fifth antenna element, and the sixth antenna element. The first antenna element, the second antenna element, the third antenna element, the fourth antenna element, the fifth antenna element, and the sixth antenna element are all substantially arranged in a first straight line.

Abstract: An antenna structure includes a loop radiation element and a first radiation element. The loop radiation element has a first end and a second end. A feeding point is positioned at the first end of the loop radiation element. A grounding point is positioned at the second end of the loop radiation element. The first radiation element has a first end and a second end. The first end of the first radiation element is coupled to a first connection point on the loop radiation element. The second end of the first radiation element is open. The antenna structure covers a first frequency band and a second frequency band.

Abstract: A multimode clutch assembly is positioned in a powertrain of a rotorcraft. The clutch assembly includes a freewheeling unit having a driving mode in which torque applied to the input race is transferred to the output race and an overrunning mode in which torque applied to the output race is not transferred to the input race. A bypass assembly has an engaged position that couples the input and output races of the freewheeling unit. An actuator assembly shifts the bypass assembly between engaged and disengaged positions. An engagement status sensor is configured to determine the engagement status of the bypass assembly. In the disengaged position, the overrunning mode of the freewheeling unit is enabled such that the clutch assembly is configured for unidirectional torque transfer. In the engaged position, the overrunning mode of the freewheeling unit is disabled such that the clutch assembly is configured for bidirectional torque transfer.

Abstract: An antenna system includes a first antenna, a second antenna, a first parasitic element, and a second parasitic element. The first antenna includes a first feeding element, a first radiation element, and a shorting element. The first radiation element is coupled to the first feeding element. The first feeding element is coupled through the shorting element to a first grounding point. The second antenna includes a second feeding element, a second radiation element, and a third radiation element. The second radiation element and the third radiation element are coupled to the second feeding element. The first parasitic element is coupled to a second grounding point. The second parasitic element is coupled to a third grounding point. The first parasitic element and the second parasitic element are disposed between the first and second antennas. The first parasitic element and the second parasitic element extend away from each other.

Abstract: A method includes forming a gate structure and an interlayer dielectric (ILD) layer over a substrate; selectively forming an inhibitor over the gate structure; performing an atomic layer deposition (ALD) process to form a dielectric layer over the ILD layer, wherein in the ALD process the dielectric layer has greater growing rate on the ILD than on the inhibitor; and performing an atomic layer etching (ALE) process to etch the dielectric layer until a top surface of the inhibitor is exposed, in which a portion of the dielectric layer remains on the ILD layer after the ALE process is complete.

Abstract: A semiconductor device includes a substrate, a first fin, a second fin, a dummy fin, a first metal gate, a second metal gate, and an isolation structure. The first, the second and the dummy fins are on the substrate, and the dummy fin is disposed between the first fin and the second fin. The first metal gate and the second metal gate are over the first fin and the second fin, respectively. The isolation structure is on the dummy fin, and the dummy fin and the isolation structure separate the first metal gate and the second metal gate.

Abstract: A semiconductor device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, an inhibitor residue over gate structure and between the gate spacers, and source/drain structures on opposite sides of the gate structure. The inhibitor residue lines a sidewall of one of the gate spacers.

Abstract: An antenna system includes a first antenna, a second antenna, a first parasitic element, and a second parasitic element. The first antenna includes a first feeding element, a first radiation element, and a shorting element. The first radiation element is coupled to the first feeding element. The first feeding element is coupled through the shorting element to a first grounding point. The second antenna includes a second feeding element, a second radiation element, and a third radiation element. The second radiation element and the third radiation element are coupled to the second feeding element. The first parasitic element is coupled to a second grounding point. The second parasitic element is coupled to a third grounding point. The first parasitic element and the second parasitic element are disposed between the first and second antennas. The first parasitic element and the second parasitic element extend away from each other.

Abstract: A multimode clutch assembly is positioned in a powertrain of a rotorcraft. The clutch assembly includes a freewheeling unit having a driving mode in which torque applied to the input race is transferred to the output race and an overrunning mode in which torque applied to the output race is not transferred to the input race. A bypass assembly has an engaged position that couples the input and output races of the freewheeling unit. An actuator assembly shifts the bypass assembly between engaged and disengaged positions. An engagement status sensor is configured to determine the engagement status of the bypass assembly. In the disengaged position, the overrunning mode of the freewheeling unit is enabled such that the clutch assembly is configured for unidirectional torque transfer. In the engaged position, the overrunning mode of the freewheeling unit is disabled such that the clutch assembly is configured for bidirectional torque transfer.

Abstract: A method includes forming a metal layer over a substrate; forming a dielectric layer over the metal layer; removing a first portion of the dielectric layer to expose a first portion of the metal layer, while a second portion of the dielectric layer remains on the metal layer; selectively forming a first inhibitor on the second portion of the dielectric layer, while the metal layer is free of coverage by the first inhibitor; and selectively depositing a first hard mask on the exposed first portion of the metal layer, while the first inhibitor is free of coverage by the first hard mask.

Abstract: A semiconductor device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, an inhibitor residue over gate structure and between the gate spacers, and source/drain structures on opposite sides of the gate structure. The inhibitor residue lines a sidewall of one of the gate spacers.

Abstract: An amplifier circuit including an input amplifier, an output amplifier and a diode device is provided. The output amplifier includes a PMOSFET and an NMOSFET. The PMOSFET has a gate electrode serving as a first input end and a drain coupled to an output end. The NMOSFET has a gate electrode serving as a second input end and a drain coupled to the output end. The output amplifier outputs an output voltage at the output end, and is coupled to the input amplifier via at least one of the first and second input ends. The diode device is coupled between the output end and the at least one of the first and second input ends of the output amplifier. When a voltage difference between the output end and the at least one of the first and second input ends of the output amplifier is greater than a barrier voltage of the diode device, the diode device is turned on, and an overshoot of the output voltage is reduced.

Abstract: An amplifier circuit including an input amplifier, an output amplifier and a diode device is provided. The output amplifier is coupled to the input amplifier and outputs an output voltage. The diode device is coupled between an output end and an input end of the output amplifier. When a voltage difference between the output end and the input end of the output amplifier is greater than a barrier voltage of the diode device, the diode device is turned on, and an overshoot of the output voltage is reduced.

Abstract: A method includes forming a metal layer over a substrate; forming a dielectric layer over the metal layer; removing a first portion of the dielectric layer to expose a first portion of the metal layer, while a second portion of the dielectric layer remains on the metal layer; selectively forming a first inhibitor on the second portion of the dielectric layer, while the metal layer is free of coverage by the first inhibitor; and selectively depositing a first hard mask on the exposed first portion of the metal layer, while the first inhibitor is free of coverage by the first hard mask.

Abstract: A method includes forming a gate stack and an interlayer dielectric (ILD) over a substrate, wherein the interlayer dielectric is adjacent to the gate stack; forming an inhibitor covering the interlayer dielectric such that the gate stack is exposed from the inhibitor; performing a deposition process to form a conductive layer over the gate stack until the conductive layer starts to form on the inhibitor, in which the deposition process has a deposition selectivity for the gate stack with respect to the inhibitor; and performing an etching process to remove a portion of the conductive layer over the inhibitor.

Abstract: An antenna system includes a dielectric substrate, a ground plane, and a first antenna array. The ground plane is disposed on a second surface of the dielectric substrate. The first antenna array is disposed on a first surface of the dielectric substrate. The first antenna array includes a first transmission line, a first antenna element, a second antenna element, a third antenna element, a fourth antenna element, a fifth antenna element, and a sixth antenna element. The first transmission line has a first feeding point and is coupled to the first antenna element, the second antenna element, the third antenna element, the fourth antenna element, the fifth antenna element, and the sixth antenna element. The first antenna element, the second antenna element, the third antenna element, the fourth antenna element, the fifth antenna element, and the sixth antenna element are all substantially arranged in a first straight line.

Abstract: A semiconductor device includes a substrate, a first fin, a second fin, a dummy fin, a first metal gate, a second metal gate, and an isolation structure. The first, the second and the dummy fins are on the substrate, and the dummy fin is disposed between the first fin and the second fin. The first metal gate and the second metal gate are over the first fin and the second fin, respectively. The isolation structure is on the dummy fin, and the dummy fin and the isolation structure separate the first metal gate and the second metal gate.

Abstract: A method includes forming a metal layer over a substrate; forming a dielectric layer over the metal layer; removing a first portion of the dielectric layer to expose a first portion of the metal layer, while a second portion of the dielectric layer remains on the metal layer; selectively forming a first inhibitor on the second portion of the dielectric layer, while the metal layer is free of coverage by the first inhibitor; and selectively depositing a first hard mask on the exposed first portion of the metal layer, while the first inhibitor is free of coverage by the first hard mask.

Abstract: A method includes forming a gate stack and an interlayer dielectric (ILD) over a substrate, wherein the interlayer dielectric is adjacent to the gate stack; forming an inhibitor covering the interlayer dielectric such that the gate stack is exposed from the inhibitor; performing a deposition process to form a conductive layer over the gate stack until the conductive layer starts to form on the inhibitor, in which the deposition process has a deposition selectivity for the gate stack with respect to the inhibitor; and performing an etching process to remove a portion of the conductive layer over the inhibitor.

Abstract: A data control circuit includes an output stage circuit, a switch circuit, and an impedance module. The output stage circuit outputs a data signal. An input terminal of the switch circuit is coupled to an output terminal of the output stage circuit, and an output terminal of the switch circuit is coupled to a post-stage circuit. According to a control of a control signal, the switch circuit determines whether to transmit the data signal of the output stage circuit to the post-stage circuit. The impedance module is configured in the output stage circuit, configured between the output stage circuit and the switch circuit, or configured in the switch circuit. Here, the impedance module reduces noise flowing from the switch circuit to the output stage circuit.