Abstract: Provided is a pharmaceutical composition including gastrodin and a use thereof for the prevention or the treatment of amyotrophic lateral sclerosis. The pharmaceutical composition is effective in reducing neuronal axon degeneration and neurofibromin accumulation, improving symptoms of amyotrophic lateral sclerosis and extending life of patients of amyotrophic lateral sclerosis.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.

Abstract: An apparatus includes a flow cell, an imaging assembly, and a processor. The flow cell includes a channel and a plurality of reaction sites. The imaging assembly is operable to receive light emitted from the reaction sites in response to an excitation light. The processor is configured to drive relative movement between at least a portion of the imaging assembly and the flow cell along a continuous range of motion to thereby enable the imaging assembly to capture images along the length of the channel. The processor is also configured to activate the imaging assembly to capture one or more calibration images of one or more calibration regions of the channel, during a first portion of the continuous range of motion. The processor is also configured to activate the imaging assembly to capture images of the reaction sites during a second portion of the continuous range of motion.

Abstract: Some implementations of the disclosure relate to an imaging system including one or more image sensors and a Z-stage. The imaging system is configured to perform operations including: capturing, using the one or more image sensors, a first image of a first pair of spots projected at a first sample location of a sample; determining whether or not the first image of the first pair of spots is valid; and when the first image is determined to be valid: obtaining, based on the first image, a current separation distance measurement of the first pair of spots; and controlling, based at least on the current separation distance measurement, the Z-stage to focus the imaging system at the first sample location.

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.

Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

Abstract: A method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked in a first direction over a substrate, the first semiconductor layers being thicker than the second semiconductor layers. The method also includes patterning the stacked structure into a first fin structure and a second fin structure extending along a second direction substantially perpendicular to the first direction. The method further includes removing the first semiconductor layers of the first fin structure to form a plurality of nanowires. Each of the nanowires has a first height, there is a distance between two adjacent nanowires along the vertical direction, and the distance is greater than the first height. The method includes forming a first gate structure between the second semiconductor layers of the first fin structure.

Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

Abstract: A method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked in a first direction over a substrate, the first semiconductor layers being thicker than the second semiconductor layers. The method also includes patterning the stacked structure into a first fin structure and a second fin structure extending along a second direction substantially perpendicular to the first direction. The method further includes removing the first semiconductor layers of the first fin structure to form a plurality of nanowires. Each of the nanowires has a first height, there is a distance between two adjacent nanowires along the vertical direction, and the distance is greater than the first height. The method includes forming a first gate structure between the second semiconductor layers of the first fin structure.

Abstract: A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate electrode surrounding at least some of the channel region. A first gate edge of the gate electrode is separated a first distance from a first type region edge of the first type region and a second gate edge of the gate electrode is separated a second distance from a second type region edge of the second type region. The first distance is less than the second distance.

Abstract: A device includes a substrate, a stacked structure and a first gate stack. The stacked structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate. One of the first semiconductor layers has a height greater than a height of one the second semiconductor layers. The first gate stack wraps around the stacked structure.

Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

Abstract: A device includes a substrate, a stacked structure and a first gate stack. The stacked structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate. One of the first semiconductor layers has a height greater than a height of one the second semiconductor layers. The first gate stack wraps around the stacked structure.

Abstract: A semiconductor device having a channel formed from a nanowire with a multi-dimensional diameter is provided. The semiconductor device comprises a drain region formed on a semiconductor substrate. The semiconductor device further comprises a nanowire structure formed between a source region and the drain region. The nanowire structure has a first diameter section joined with a second diameter section. The first diameter section is coupled to the drain region and has a diameter greater than the diameter of the second diameter section. The second diameter section is coupled to the source region. The semiconductor device further comprises a gate region formed around the junction at which the first diameter section and the second diameter section are joined.

Abstract: A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate electrode surrounding at least some of the channel region. A first gate edge of the gate electrode is separated a first distance from a first type region edge of the first type region and a second gate edge of the gate electrode is separated a second distance from a second type region edge of the second type region. The first distance is less than the second distance.

Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

Abstract: A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate electrode surrounding at least some of the channel region. A first gate edge of the gate electrode is separated a first distance from a first type region edge of the first type region and a second gate edge of the gate electrode is separated a second distance from a second type region edge of the second type region. The first distance is less than the second distance.

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed having a gate dielectric and a gate electrode in the opening. A dielectric material is formed abutting the portion of the gate structure.

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed having a gate dielectric and a gate electrode in the opening. A dielectric material is formed abutting the portion of the gate structure.