Patents by Inventor Chia Wen Liu

Chia Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10361234
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Chia-Chieh Lin, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 10355149
    Abstract: A tandem solar cell module includes a transparent substrate, a first solar cell unit, and a second solar cell unit disposed between the transparent substrate and the first solar cell unit. The first solar cell unit includes a first electrode, a second electrode, and a first absorption layer disposed between the first electrode and the second electrode, and the second solar cell unit includes a third electrode, a fourth electrode, and a second absorption layer disposed between the third electrode and the fourth electrode, wherein the second electrode is located adjacent to the third electrode, and the positions of the second electrode, the third electrode, and the fourth electrode are corresponding to each other.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: July 16, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Chia-Wen Chang, Yung-Tsung Liu, Wei-Sheng Lin
  • Patent number: 10332942
    Abstract: An OLED touch display device includes a first electrode layer, a second electrode layer facing the first electrode layer, a light-emitting layer between the first electrode layer and the second electrode, and a third electrode layer on a side of the first electrode layer. The first electrode layer functions as a cathode of the light-emitting layer, and the second electrode layer functions as an anode of the light-emitting layer. The first electrode layer and the third electrode layer cooperatively form a capacitive force sensing element. The first electrode layer also functions as touch sensing electrode.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: June 25, 2019
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Fu Weng, Chien-Wen Lin, Chia-Lin Liu
  • Patent number: 10324556
    Abstract: A touch display apparatus a display unit and a touch unit. The display unit displays images and the touch unit which is overlapped on the display unit can sense independently a touch action applied on the touch unit and also the pressure applied in such touch. The touch display apparatus virtually simultaneously operates under a display period and a touch period in one frame for improving accuracy of determining the aspects of a touch function.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: June 18, 2019
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Fu Weng, Chia-Lin Liu, Chien-Wen Lin
  • Patent number: 10303310
    Abstract: An in-cell touch display apparatus includes a substrate structure, a display driving integrated chip (IC), and a plurality of touch sensor units arranged in a matrix. Each of the touch sensor units includes a plurality of connecting lines of difference lengths and a plurality of compensating portions corresponding to the connecting lines in a one-to-one relationship. Each of the connecting lines establishes an electrical connection between the touch sensor unit and the display driving IC. The compensating portions are electrically connected to the display driving IC. The connecting lines and the compensating portions receive a common voltage from the display driving IC during the display period. A sum of the lengths of the connecting line and the compensating portion is constant throughout the plurality of connecting lines so as to compensate for different capacitances of the connecting lines.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: May 28, 2019
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Fu Weng, Chien-Wen Lin, Chia-Lin Liu
  • Patent number: 10296152
    Abstract: A touch display device includes a display module and a sensing module on the display module. The sensing module includes a first electrode layer on the display module, a second electrode layer facing the first electrode layer, and a dielectric layer between the first electrode layer and the second electrode layer. The second electrode layer includes a plurality of electrodes. The electrodes functions as electrodes of the touch display device for sensing a touch position. The electrodes, the first electrode layer, and the dielectric layer cooperatively form capacitors for sensing a touch force.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: May 21, 2019
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Fu Weng, Chien-Wen Lin, Chia-Lin Liu
  • Publication number: 20190131274
    Abstract: A device includes a substrate, a stacked structure and a first gate stack. The stacked structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate. One of the first semiconductor layers has a height greater than a height of one the second semiconductor layers. The first gate stack wraps around the stacked structure.
    Type: Application
    Filed: October 26, 2017
    Publication date: May 2, 2019
    Inventors: Zhi-Qiang WU, Chun-Fu CHENG, Chung-Cheng WU, Yi-Han WANG, Chia-Wen LIU
  • Patent number: 10276664
    Abstract: A semiconductor device having a channel formed from a nanowire with a multi-dimensional diameter is provided. The semiconductor device comprises a drain region formed on a semiconductor substrate. The semiconductor device further comprises a nanowire structure formed between a source region and the drain region. The nanowire structure has a first diameter section joined with a second diameter section. The first diameter section is coupled to the drain region and has a diameter greater than the diameter of the second diameter section. The second diameter section is coupled to the source region. The semiconductor device further comprises a gate region formed around the junction at which the first diameter section and the second diameter section are joined.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Hsing Yu, Chia-Wen Liu, Yeh Hsu, Jean-Pierre Colinge
  • Publication number: 20180323284
    Abstract: A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate electrode surrounding at least some of the channel region. A first gate edge of the gate electrode is separated a first distance from a first type region edge of the first type region and a second gate edge of the gate electrode is separated a second distance from a second type region edge of the second type region. The first distance is less than the second distance.
    Type: Application
    Filed: June 29, 2018
    Publication date: November 8, 2018
    Inventors: Jean-Pierre COLINGE, Carlos H. DIAZ, Yeh HSU, Tsung-Hsing YU, Chia-Wen LIU
  • Publication number: 20180301560
    Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 18, 2018
    Inventors: Huan-Sheng WEI, Hung-Li CHIANG, Chia-Wen LIU, Yi-Ming SHEU, Zhiqiang WU, Chung-Cheng WU, Ying-Keung LEUNG
  • Patent number: 10026826
    Abstract: A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate electrode surrounding at least some of the channel region. A first gate edge of the gate electrode is separated a first distance from a first type region edge of the first type region and a second gate edge of the gate electrode is separated a second distance from a second type region edge of the second type region. The first distance is less than the second distance.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: July 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Jean-Pierre Colinge, Carlos H. Diaz, Yeh Hsu, Tsung-Hsing Yu, Chia-Wen Liu
  • Patent number: 10008603
    Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed having a gate dielectric and a gate electrode in the opening. A dielectric material is formed abutting the portion of the gate structure.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huan-Sheng Wei, Hung-Li Chiang, Chia-Wen Liu, Yi-Ming Sheu, Zhiqiang Wu, Chung-Cheng Wu, Ying-Keung Leung
  • Publication number: 20180145176
    Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed having a gate dielectric and a gate electrode in the opening. A dielectric material is formed abutting the portion of the gate structure.
    Type: Application
    Filed: November 18, 2016
    Publication date: May 24, 2018
    Inventors: Huan-Sheng WEI, Hung-Li CHIANG, Chia-Wen LIU, Yi-Ming SHEU, Zhiqiang WU, Chung-Cheng WU, Ying-Keung LEUNG
  • Patent number: 9929245
    Abstract: Semiconductor devices and methods for forming semiconductor devices are provided. A vertical channel structure extends from a substrate and is formed as a channel between a source region and a drain region. A first metal gate surrounds a portion of the vertical channel structure and has a gate length. The first metal gate has a first gate section with a first workfunction and a first thickness. The first metal gate also has a second gate section with a second workfunction and a second thickness. The first thickness is different from the second thickness, and the sum of the first thickness and the second thickness is equal to the gate length. A ratio of the first thickness to the second thickness is chosen to achieve a desired threshold voltage level for the semiconductor device.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: March 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Chia-Wen Liu, Wei-Hao Wu, Chih-Hao Wang, Carlos H. Diaz
  • Patent number: 9837533
    Abstract: Some embodiments of the present disclosure provide a semiconductor structure, including a substrate and a regrowth region. The substrate is made of a first material with a first lattice constant, and the regrowth region is made of the first material and a second material, having a lattice constant different from the first lattice constant. The regrowth region is partially positioned in the substrate. The regrowth region has a “tip depth” measured vertically from a surface of the substrate to a widest vertex of the regrowth region, and the tip depth being less than 10 nm. The regrowth region further includes a top layer substantially made of the first material, and the top layer has substantially the first lattice constant.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: December 5, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Jiun Kuang, Tsung-Hsing Yu, Yi-Ming Sheu, Chun-Yi Lee, Chia-Wen Liu
  • Patent number: 9768297
    Abstract: The present disclosure relates to a transistor device having an epitaxial carbon layer and/or a carbon implantation region that provides for a low variation of voltage threshold, and an associated method of formation. In some embodiments, the transistor device has an epitaxial region arranged within a recess within a semiconductor substrate. The epitaxial region has a carbon doped silicon epitaxial layer and a silicon epitaxial layer disposed onto the carbon doped silicon epitaxial layer. A gate structure is arranged over the silicon epitaxial layer. The gate structure has a gate dielectric layer disposed onto the silicon epitaxial layer and a gate electrode layer disposed onto the gate dielectric layer. A source region and a drain region are arranged on opposing sides of a channel region disposed below the gate structure.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsing Yu, Chia-Wen Liu, Yeh Hsu, Shih-Syuan Huang, Ken-Ichi Goto, Zhiqiang Wu
  • Patent number: 9728602
    Abstract: A semiconductor device includes a nanowire structure and a stressor. The nanowire structure includes a first channel section and a second channel section. The stressor subjects the first channel section to a first strain level and the second channel section to a second strain level greater than the first strain level. The difference between the second strain level and the first strain level is less than the second strain level.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: August 8, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Hsing Yu, Yeh Hsu, Chia-Wen Liu, Jean-Pierre Colinge
  • Patent number: 9716172
    Abstract: A semiconductor device and method of forming the same are described. A semiconductor device includes an active area adjacent a channel in a semiconductor composite. The active area includes a first active area layer having a first dopant concentration, a second active area layer having a second dopant concentration over the first active area layer, and a third active area layer having a third dopant concentration, over the second active area. The third dopant concentration is greater than the second dopant concentration, and the second dopant concentration is greater than the first dopant concentration. The channel includes a second channel layer comprising carbon over a first channel layer and a third channel layer over the second channel layer. The active area configuration improves drive current and reduces contact resistance, and the channel configuration increases short channel control, as compared to a semiconductor device without the active area and channel configuration.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: July 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Hsing Yu, Chia-Wen Liu, Yeh Hsu, Ken-Ichi Goto
  • Patent number: 9660049
    Abstract: A transistor and a method for forming the transistor are provided. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile has high dopant impurity concentration areas at opposed ends of the transistor channel.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsing Yu, Chia-Wen Liu, Ken-Ichi Goto
  • Patent number: 9653545
    Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mahaveer Sathaiya Dhanyakumar, Wei-Hao Wu, Tsung-Hsing Yu, Chia-Wen Liu, Tzer-Min Shen, Ken-Ichi Goto, Zhiqiang Wu