Patents by Inventor Chia-Yang Wu

Chia-Yang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200331038
    Abstract: Debris is removed from a collector of an extreme ultraviolet light source vessel by applying a suction force through a vacuum opening of a cable. The method for removing debris also includes weakening debris attachment by using a sticky surface or by spreading a solution through a nozzle, wherein the sticky surface and the nozzle are arranged on the cable proximal to the vacuum opening. A borescope system and interchangeable rigid portions of the cable assists in targeting a target area of the collector where the debris is.
    Type: Application
    Filed: April 18, 2019
    Publication date: October 22, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shang-Ying WU, Ming-Hsun TSAI, Sheng-Kang YU, Yung-Teng YU, Chi YANG, Shang-Chieh CHIEN, Chia-Chen CHEN, Li-Jui CHEN, Po-Chung CHENG
  • Patent number: 10781266
    Abstract: An antibody, or an antigen-binding fragment there, binding human ENO1 (GenBank: AAH506421.1) is provided. Methods for treating an ENO1 protein-related disease or disorder, inhibiting cancer invasion and diagnosis of cancer are also provided.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: September 22, 2020
    Assignees: DEVELOPMENT CENTER FOR BIOTECHNOLOGY, NATIONAL HEALTH RESEARCH INSTITUTES
    Inventors: Shih-Chong Tsai, Ta-Tung Yuan, Shih-Chi Tseng, Jiann-Shiun Lai, Chia-Cheng Wu, Po-Yin Lin, Ya-Wei Tsai, Chao-Yang Huang, Ying-Yung Lok, Chung-Hsiun Wu, Hsien-Yu Tsai, Neng-Yao Shih, Ko-Jiunn Liu, Li-Tzong Chen
  • Patent number: 10763338
    Abstract: The present disclosure describes a silicide formation process which employs the formation of an amorphous layer in the SiGe S/D region via an application of a substrate bias voltage during a metal deposition process. For example, the method includes a substrate with a gate structure disposed thereon and a source/drain region adjacent to the gate structure. A dielectric is formed over the gate structure and the source-drain region. A contact opening is formed in the dielectric to expose a portion of the gate structure and a portion of the source/drain region. An amorphous layer is formed in the exposed portion of the source/drain region with a thickness and a composition which is based on an adjustable bias voltage applied to the substrate. Further, an anneal is performed to form a silicide on the source/drain region.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yang Wu, Shiu-Ko Jang-Jian, Ting-Chun Wang, Chuan-Pu Liu
  • Publication number: 20200266069
    Abstract: A device includes a source/drain (S/D) in a substrate and adjacent to a gate structure, wherein the S/D comprises a protrusion extending from a top surface of the S/D, and the protrusion has a tapered profile. The device further includes a contact plug electrically connected to the protrusion.
    Type: Application
    Filed: May 7, 2020
    Publication date: August 20, 2020
    Inventors: Chia-Yang WU, Shiu-Ko JANGJIAN, Keng-Chuan CHANG, Ting-Siang SU
  • Publication number: 20200251577
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor over a substrate. The semiconductor device structure includes a dielectric structure over the substrate and covering the transistor. The semiconductor device structure includes a contact structure passing through the dielectric structure and electrically connected to the transistor. The contact structure includes a contact layer, a first barrier layer, and a second barrier layer, the first barrier layer surrounds the contact layer, the second barrier layer surrounds a first upper portion of the first barrier layer, a first lower portion of the first barrier layer is in direct contact with the dielectric structure, and a thickness of the first lower portion increases toward the substrate.
    Type: Application
    Filed: April 20, 2020
    Publication date: August 6, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yang WU, Shiu-Ko JANGJIAN, Ting-Chun WANG, Yung-Si YU
  • Publication number: 20200243664
    Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided, in which the method includes the steps of forming a gate structure on a substrate, forming a spacer on a sidewall of the gate structure, forming two recesses adjacent to two sides of the spacer, performing a cleaning process to trim the spacer for forming a void between the spacer and the substrate, and forming two portions of an epitaxial layer in the two recesses. The semiconductor device preferably includes a cap layer on the two portions of the epitaxial layer as the cap layer includes a planar top surface and an inclined sidewall.
    Type: Application
    Filed: March 6, 2019
    Publication date: July 30, 2020
    Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
  • Patent number: 10714576
    Abstract: A device includes an epitaxy structure having a recess therein, a dielectric layer over the epitaxy structure, the dielectric layer having a contact hole communicating with the recess, a dielectric spacer liner (DSL) layer on a sidewall of the recess, a barrier layer on the DSL layer, and a conductor. The DSL layer has an opening. The DSL layer extends further into the epitaxy structure than the barrier layer. The conductor is disposed in the contact hole and electrically connected to the epitaxy feature through the opening of the DSL layer.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Cheng Hung, Kei-Wei Chen, Yu-Sheng Wang, Ming-Ching Chung, Chia-Yang Wu
  • Publication number: 20200167957
    Abstract: Correction method and device for an eye-tracker are provided. A non-predetermined scene frame is provided and analyzed to obtain a salient feature information, which is in-turn used to correct an eye-tracking operation. The correction can be done at the initial or during the wearing of an eye-tracker.
    Type: Application
    Filed: March 11, 2019
    Publication date: May 28, 2020
    Inventors: Shao-Yi Chien, Chia-Yang Chang, Shih-Yi Wu
  • Patent number: 10658186
    Abstract: A method of forming a semiconductor device includes depositing a titanium-containing material over a source/drain (S/D), wherein an energy of depositing the titanium-containing material is sufficient to cause re-deposition of a material of the S/D along sidewalls of a dielectric layer adjacent the S/D to form protrusions extending from a top surface of the S/D. The method further includes annealing the semiconductor device to form a silicide layer in the S/D and in the protrusions.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Yang Wu, Shiu-Ko Jangjian, Keng-Chuan Chang, Ting-Siang Su
  • Patent number: 10629708
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric structure over a transistor. The method includes forming a first recess in the dielectric structure. The method includes forming a first barrier layer over a first inner wall of the first recess. The first barrier layer has a first opening over a first portion of the dielectric structure, and the first barrier layer close to a first bottom surface of the first recess is thicker than the first barrier layer close to a top surface of the dielectric structure. The method includes removing the first portion through the first opening to form a second recess in the dielectric structure. The method includes forming a second barrier layer over a second inner wall of the second recess. The method includes forming a contact layer in the first opening and the second opening.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yang Wu, Shiu-Ko Jangjian, Ting-Chun Wang, Yung-Si Yu
  • Patent number: 10588244
    Abstract: A temperature-regulated cabinet (10) includes a cabinet body (1) and a temperature regulating module (2). The cabinet body (1) has a containing space (11) formed inside the cabinet body (1) and an opening (12) communicated with the containing space (11). The temperature regulating module (2) is detachably installed to the cabinet body (1) and covered onto the opening (12) and includes a temperature regulator (21), a first hood (22), a second hood (23) and an exhaust fan (24). The temperature regulator (21) has a casing (211). The first hood (22) is detachably installed to the top of the casing (211), and the second hood (23) is detachably installed to the bottom of the casing (211). The exhaust fan (24) is installed inside the first hood (22) or the second hood (23). The cabinet has the advantages of simplifying the production line and lowering the construction and operation costs.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: March 10, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Lee-Long Chen, Chia-Wei Chen, Jian-Jhang Wu, Chun-Yang Hung
  • Patent number: 10558334
    Abstract: An electronic device, a method and a non-transitory computer-readable medium of messaging are disclosed herein. The electronic device includes at least one processor, a touch-sensitive module, a display module and a non-transitory computer-readable medium. The non-transitory computer-readable medium includes one or more sequences of instructions to be executed by the processor for performing a messaging method. The messaging method includes the following steps: sensing a touch corresponding to a first contact icon displayed on the display module; counting a time duration of the touch; recording a message when the time duration exceeds a first predetermined time period; and sending the message according to contact information corresponding to the first contact icon.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: February 11, 2020
    Assignee: HTC Corporation
    Inventors: Chia-Chia Shieh, Yen-Shun Wu, Shih-Hsun Ou, Ting-An Yang
  • Publication number: 20200043858
    Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Inventors: Chia-Yang Wu, Shiu-Ko JangJian, Ting-Chun Wang, Yung-Si Yu
  • Publication number: 20190391633
    Abstract: A power saving method includes enabling an input signal detection unit of the display controller for detecting a first presence of at least one input signal of the display controller, entering the display controller to a power-off mode temporarily for decreasing an operation power from a first power to a second power within a second time period when the at least one input signal is not received by the input signal detection unit within a first time period, detecting a second presence of the at least one input signal continuously by the input signal detection unit after the second time period elapses, and adjusting an operation mode of the display controller according to the second presence of the at least one input signal. The second power is smaller than the first power. The second power corresponds to a power of the display controller under the power-off mode.
    Type: Application
    Filed: May 6, 2019
    Publication date: December 26, 2019
    Inventors: Kao-Yang Wu, Chia-Hsiung Kuo
  • Publication number: 20190322762
    Abstract: An antibody, or an antigen-binding fragment there, binding human ENO1 (GenBank: AAH506421.1) is provided. Methods for treating an ENO1 protein-related disease or disorder, inhibiting cancer invasion and diagnosis of cancer are also provided.
    Type: Application
    Filed: March 19, 2018
    Publication date: October 24, 2019
    Applicants: DEVELOPMENT CENTER FOR BIOTECHNOLOGY, NATIONAL HEALTH RESEARCH INSTITUTES
    Inventors: SHIH-CHONG TSAI, TA-TUNG YUAN, SHIH-CHI TSENG, JIANN-SHIUN LAI, CHIA-CHENG WU, PO-YIN LIN, YA-WEI TSAI, CHAO-YANG HUANG, YING-YUNG LOK, CHUNG-HSIUN WU, HSIEN-YU TSAI, NENG-YAO SHIH, KO-JIUNN LIU, LI-TZONG CHEN
  • Patent number: 10454112
    Abstract: An anode and a lithium ion battery employing the same are provided. The anode includes a lithium-containing layer and a single-ion conductive layer. The single-ion conductive layer includes an inorganic particle, a single-ion conductor polymer, and a binder. The single-ion conductor polymer has a first repeat unit of Formula (I), a second repeat unit of Formula (II), a third repeat unit of Formula (III), and a fourth repeat unit of Formula (IV) wherein R1 is O?M+, SO3?M+, N(SO2F)?M+, N(SO2CF3)?M+, N(SO2CF2CF3)?M+, COO?M+, or PO4?M+; M+ is Li+, Na+, K+, Cs+, or a combination thereof; and R2 is CH3, CH2CH3, or CH2CH2OCH2CH3. In particular, the weight ratio of the inorganic particle to the sum of the single-ion conductor polymer and the binder is from 4:1 to 9:1, and the weight ratio of the binder to the single-ion conductor polymer is from 1:1 to 9:1.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 22, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wei-Hsin Wu, Sheng-Hui Wu, Chi-Yang Chao, Kun-Lin Liu, Chia-Chen Fang
  • Publication number: 20190309092
    Abstract: The present invention provides a modified antigen-binding Fab fragment. An antigen-binding molecule comprising the antigen-binding Fab fragment and a composition comprising the molecule are also provided.
    Type: Application
    Filed: July 20, 2017
    Publication date: October 10, 2019
    Applicant: Development Center for Biotechnology
    Inventors: Chih-Yung HU, Chao-Yang HUANG, Yu-Jung CHEN, Chia-Cheng WU, Chien-Tsun KUAN, Chia-Hsiang LO, Hsien-Yu TSAI
  • Patent number: 10408246
    Abstract: A receiving device for an electronic device, to hold a stylus, includes a top member, a bottom member, and a connection member. The bottom member faces the top member, the connection member is arranged between the top member and the bottom member. A clamping member and a receiving member are formed between the top member, the bottom member, and the connection member. The clamping member faces away from the receiving member, the clamping member is clamped onto an electronic device, the receiving member receives a stylus.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: September 10, 2019
    Assignees: Fu Tai Industry (Shenzhen) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Lei Hu, Chia-Jui Hu, Hao-Yuan Huang, Yen-Yu Chen, Chun-Kai Peng, Jian-Guo Wu, Xin Yang
  • Patent number: 10396196
    Abstract: A semiconductor device includes a substrate, a semiconductor layer, a doped region, a device region, a first isolation structure, a second isolation structure and a terminal. The semiconductor layer is disposed over the substrate. The doped region is disposed in the semiconductor layer. The device region is disposed on the doped region and includes a source, a drain and a gate. The first isolation structure is disposed in the semiconductor layer and surrounds the doped region. The second isolation structure surrounds the first isolation structure and is spaced apart from the first isolation structure. The terminal is disposed between the first isolation structure and the second isolation structure, and is equipotential with the source.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: August 27, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jui-Chun Chang, Shih-Kai Wu, Cheng-Yu Wang, Li-Yang Hong, Chia-Ming Hsu
  • Publication number: 20190207222
    Abstract: An anode and a lithium ion battery employing the same are provided. The anode includes a lithium-containing layer and a single-ion conductive layer. The single-ion conductive layer includes an inorganic particle, a single-ion conductor polymer, and a binder. The single-ion conductor polymer has a first repeat unit of Formula (I), a second repeat unit of Formula (II), a third repeat unit of Formula (III), and a fourth repeat unit of Formula (IV) wherein R1 is O?M+, SO3?M?, N(SO2F)?M+, N(SO2CF3)?M+, N(SO2CF2CF3)?M+, COO?M+, or PO4?M+; M+ is Li+, Na+, K+, Cs+, or a combination thereof; and R2 is CH3, CH2CH3, or CH2CH2OCH2CH3. In particular, the weight ratio of the inorganic particle to the sum of the single-ion conductor polymer and the binder is from 4:1 to 9:1, and the weight ratio of the binder to the single-ion conductor polymer is from 1:1 to 9:1.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Wei-Hsin WU, Sheng-Hui WU, Chi-Yang CHAO, Kun-Lin LIU, Chia-Chen FANG