Abstract: A method of forming a semiconductor device includes depositing a titanium-containing material over a source/drain (S/D), wherein an energy of depositing the titanium-containing material is sufficient to cause re-deposition of a material of the S/D along sidewalls of a dielectric layer adjacent the S/D to form protrusions extending from a top surface of the S/D. The method further includes annealing the semiconductor device to form a silicide layer in the S/D and in the protrusions.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric structure over a transistor. The method includes forming a first recess in the dielectric structure. The method includes forming a first barrier layer over a first inner wall of the first recess. The first barrier layer has a first opening over a first portion of the dielectric structure, and the first barrier layer close to a first bottom surface of the first recess is thicker than the first barrier layer close to a top surface of the dielectric structure. The method includes removing the first portion through the first opening to form a second recess in the dielectric structure. The method includes forming a second barrier layer over a second inner wall of the second recess. The method includes forming a contact layer in the first opening and the second opening.

Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.

Abstract: A method of forming a semiconductor device includes depositing a titanium-containing material over a source/drain (S/D), wherein an energy of depositing the titanium-containing material is sufficient to cause re-deposition of a material of the S/D along sidewalls of a dielectric layer adjacent the S/D to form protrusions extending from a top surface of the S/D. The method further includes annealing the semiconductor device to form a silicide layer in the S/D and in the protrusions.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric structure over a transistor. The method includes forming a first recess in the dielectric structure. The method includes forming a first barrier layer over a first inner wall of the first recess. The first barrier layer has a first opening over a first portion of the dielectric structure, and the first barrier layer close to a first bottom surface of the first recess is thicker than the first barrier layer close to a top surface of the dielectric structure. The method includes removing the first portion through the first opening to form a second recess in the dielectric structure. The method includes forming a second barrier layer over a second inner wall of the second recess. The method includes forming a contact layer in the first opening and the second opening.

Abstract: The present disclosure describes a silicide formation process which employs the formation of an amorphous layer in the SiGe S/D region via an application of a substrate bias voltage during a metal deposition process. For example, the method includes a substrate with a gate structure disposed thereon and a source/drain region adjacent to the gate structure. A dielectric is formed over the gate structure and the source-drain region. A contact opening is formed in the dielectric to expose a portion of the gate structure and a portion of the source/drain region. An amorphous layer is formed in the exposed portion of the source/drain region with a thickness and a composition which is based on an adjustable bias voltage applied to the substrate. Further, an anneal is performed to form a silicide on the source/drain region.

Abstract: A method of forming a semiconductor device includes etching an inter-layer dielectric (ILD) to form a contact opening exposing a portion of a source/drain (S/D). The method further includes depositing a titanium-containing material into the contact opening, wherein an energy of depositing the titanium-containing material is sufficient to cause re-deposition of a material of the S/D along sidewalls of the ILD to form protrusions extending from a top surface of the S/D. The method further includes annealing the semiconductor device to form a silicide layer in the S/D and in the protrusions.

Abstract: A device includes an epitaxy structure having a recess therein, a dielectric layer over the epitaxy structure, the dielectric layer having a contact hole communicating with the recess, a dielectric spacer liner (DSL) layer on a sidewall of the recess, a barrier layer on the DSL layer, and a conductor. The DSL layer has an opening. The DSL layer extends further into the epitaxy structure than the barrier layer. The conductor is disposed in the contact hole and electrically connected to the epitaxy feature through the opening of the DSL layer.

Abstract: A method of forming a semiconductor device includes etching an inter-layer dielectric (ILD) to form a contact opening exposing a portion of a source/drain (S/D). The method further includes depositing a titanium-containing material into the contact opening, wherein an energy of depositing the titanium-containing material is sufficient to cause re-deposition of a material of the S/D along sidewalls of the ILD to form protrusions extending from a top surface of the S/D. The method further includes annealing the semiconductor device to form a silicide layer in the S/D and in the protrusions.

Abstract: A semiconductor structure includes a semiconductor substrate, at least one dielectric layer, a dielectric spacer liner (DSL) layer, and at least one conductor. The dielectric layer is present on the semiconductor substrate. The dielectric layer has at least one contact hole exposing at least a portion of the semiconductor substrate. The semiconductor substrate has at least one recess communicating with the contact hole. The recess has a bottom surface and at least one sidewall. The DSL layer is present on at least the sidewall of the recess. The conductor is present at least partially in the contact hole and is electrically connected to the semiconductor substrate.

Abstract: A semiconductor structure includes a semiconductor substrate, at least one dielectric layer, a dielectric spacer liner (DSL) layer, and at least one conductor. The dielectric layer is present on the semiconductor substrate. The dielectric layer has at least one contact hole exposing at least a portion of the semiconductor substrate. The semiconductor substrate has at least one recess communicating with the contact hole. The recess has a bottom surface and at least one sidewall. The DSL layer is present on at least the sidewall of the recess. The conductor is present at least partially in the contact hole and is electrically connected to the semiconductor substrate.

Abstract: In the present invention, the pure Cu film is deposited on the CuMn film and the Mn atoms are induced to diffuse within the dielectric layer. The barrier properties of this self-forming barrier are sensitive to the thickness, the annealing temperature, the annealing time and the impurity concentration of itself. The bi-layer structure reduces the resistance of the barrier and improves the surface morphology during the electroplating process because the Mn atoms will be more easily corroded and oxidized in sulfuric acid with respect to the Cu. After annealing, the thermal stability and the barrier properties of the Cu/CuMn films is better than either single Cu film or single CuMn film.

Abstract: A self-forming barrier structure and a semiconductor device using the same are disclosed. The self-forming barrier structure includes a silicon-containing substrate; a first barrier layer formed on the silicon-containing substrate; and a second barrier layer formed of a copper-containing alloy on the first barrier layer; wherein the copper-containing alloy comprises copper and at least one other metal which diffuses faster than copper and is not inter-miscible with copper.

Abstract: A method for forming a damascene structure. An insulating layer is deposited on a substrate. A capping layer and a hard mask layer are successively formed on the insulating layer. Subsequently, the hard mask layer is etched to form at least one opening using the capping layer as an etching stop layer. A conformable metal layer is formed over the hard mask layer and the surface of the opening, and the metal layer is then anisotropically etched to form a metal spacer over the sidewall of the opening. Next, the capping layer and the underlying insulating layer under the opening are etched to form a trench therein. Next, the hard mask layer and the metal spacer are removed. Finally, the trench is filled with the conductive layer to complete the damascene structure after the substrate is cleaned.