Patents by Inventor Chia-Yen Lee
Chia-Yen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150348889Abstract: A semiconductor device includes a lead frame, a first semiconductor component, a second semiconductor component, and a first conductive member. The lead frame includes a first segment having a first bottom plate, and a second segment having a second bottom plate. The first segment and the second segment are arranged side by side, the first bottom plate is spatially isolated from the second bottom plate, and the first bottom plate is thicker than the second bottom plate. The first semiconductor component is disposed on the first bottom plate, and the second semiconductor component is disposed on the second bottom plate. The second semiconductor component is thicker than the first semiconductor component. The first conductive member electrically connects the second semiconductor component to the first segment.Type: ApplicationFiled: May 30, 2014Publication date: December 3, 2015Applicant: DELTA ELECTRONICS, INC.Inventors: Hsin-Chang TSAI, Chia-Yen LEE, Peng-Hsin LEE
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Patent number: 9201247Abstract: Disclosed is an image display apparatus, including a display device displaying right-eye images and left-eye images. A light-modulating device attached to the display device; and a temperature sensor monitoring the light-modulating device temperature. The light-modulating device deflects the right-eye and left-eye images to an observer's right and left eyes respectively without a temperature variation in the temperature sensor.Type: GrantFiled: December 12, 2012Date of Patent: December 1, 2015Assignee: DELTA ELECTRONICS, INC.Inventors: Yeong-Feng Wang, Ching-Tung Hsu, Yen-I Chou, Chia-Yen Lee, Meng-Han Liu, Ming-Wei Tsai
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Patent number: 9184111Abstract: A wafer-level chip scale package is disclosed, including a chip including a substrate and a GaN transistor disposed on the substrate. The GaN transistor includes a first electrode, a dielectric layer disposed on the chip, and a redistribution trace disposed on the first dielectric layer and electrically connected with the first electrode, wherein the redistribution trace has a linear side and a curved side on opposite sides along its longitudinal direction.Type: GrantFiled: May 29, 2014Date of Patent: November 10, 2015Assignee: DELTA ELECTRONICS, INC.Inventors: Chia-Yen Lee, Chi-Cheng Lin, Hsin-Chang Tsai
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Patent number: 9177957Abstract: An embedded packaging device is provided, including a leadframe, a first semiconductor component, a second semiconductor component, a passive component, and a first dielectric layer. The leadframe forms a counterbore. The first semiconductor component is disposed on the leadframe. The second semiconductor component is disposed on the leadframe and electrically connected with the first semiconductor component through the leadframe. The passive component is disposed on the leadframe and has a different thickness from the first semiconductor component, wherein the passive component or the first semiconductor component is disposed in the counterbore of the leadframe, such that a top surface of the passive component has the same height as that of the first semiconductor component. The first dielectric layer is formed on the leadframe and covers the first semiconductor component, the second semiconductor component, and the passive component.Type: GrantFiled: October 16, 2014Date of Patent: November 3, 2015Assignee: DELTA ELECTRONICS, INC.Inventors: Peng Hsin Lee, Hsin Chang Tsai, Chia Yen Lee
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Patent number: 9159699Abstract: An interconnection structure is provided having a substrate with at least one electric device formed adjacent to a first side of the substrate and a via hole formed therethrough. The via hole has a first opening adjacent to the first side of the substrate. A via structure is disposed in the via hole without exceeding the first opening. A first pad is disposed on the first side of the substrate and covers the via hole. A second pad is disposed on a second side of the substrate opposite to the first side, wherein the via structure extends into the second pad. The first pad is adjoined to the via structure and electrically connects with the at least one electric device, and the first pad has a protrusion portion extending into the via hole.Type: GrantFiled: November 13, 2012Date of Patent: October 13, 2015Assignee: DELTA ELECTRONICS, INC.Inventors: Hsin-Chang Tsai, Chia-Yen Lee, Peng-Hisn Lee
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Publication number: 20150154869Abstract: A blind spot detecting system for a vehicle includes an indicating module, a blind spot detecting module, and a controlling module. The indicating module includes at least one motor that is electronically coupled to the blind spot detecting module. The blind spot detecting module is configured to detect a presence or impending presence of an object in a side lane next to the vehicle, and generate a detecting signal in response to detecting the presence or impending presence of the object. The controlling module is electronically coupled to the blind spot detecting module, and configured to control the blind spot detecting module to output the detecting signal to activate the at least one motor to vibrate.Type: ApplicationFiled: November 17, 2014Publication date: June 4, 2015Inventor: CHIA-YEN LEE
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Publication number: 20150129892Abstract: A wafer-level chip scale package is disclosed, including a chip including a substrate and a GaN transistor disposed on the substrate. The GaN transistor includes a first electrode, a dielectric layer disposed on the chip, and a redistribution trace disposed on the first dielectric layer and electrically connected with the first electrode, wherein the redistribution trace has a linear side and a curved side on opposite sides along its longitudinal direction.Type: ApplicationFiled: May 29, 2014Publication date: May 14, 2015Applicant: DELTA ELECTRONICS, INC.Inventors: Chia-Yen LEE, Chi-Cheng LIN, Hsin-Chang TSAI
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Publication number: 20150125995Abstract: A package structure including: a first semiconductor device including a first semiconductor substrate and a first electronic device, the first semiconductor device having a first side and a second side, wherein at least part of the first electronic device being adjacent to the first side, and the first semiconductor device has a via-hole formed through the first semiconductor device, wherein the via-hole has a first opening adjacent to the first side; an interconnection structure disposed in the first semiconductor device, wherein the interconnection structure includes: a via structure disposed in the via-hole without exceeding the first opening; a first pad disposed on the first side of the first semiconductor device and covering the via-hole; and a second semiconductor device vertically integrated with the first semiconductor device.Type: ApplicationFiled: January 7, 2015Publication date: May 7, 2015Inventors: Chia-Yen LEE, Hsin-Chang TSAI, Peng-Hsin LEE
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Publication number: 20150061843Abstract: A remote key for control of a vehicle includes a touch panel, a storage device, a touch sensing unit, and a micro controller. Function icons arranged on the touch panel are operable to control a vehicle to perform a function. The storage device can store coordinates of the function icons and a mapping list defining a relationship between predetermined touches and predetermined functions. The touch sensing unit can sense user touches applied to the touch panel. If the micro controller determines that a sensed touch matches one of the predetermined touches, the micro controller can further search the mapping list to determine a function corresponding to the sensed touch, and generate a remote control signal for controlling the vehicle to execute the function.Type: ApplicationFiled: August 22, 2014Publication date: March 5, 2015Inventor: CHIA-YEN LEE
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Publication number: 20150001727Abstract: The disclosure provides an embedded package structure comprising a metal substrate, a chip module, an insulation material layer, and at least one patterned metal layer. The metal substrate has a first surface and a second surface. The chip module is disposed on the first surface of the metal substrate, and comprises at least two stacked chips being electrically connected to each. The insulation material layer covers the first surface of the metal substrate and the stacked chips and has an electrical interconnection formed therein. The patterned metal layer is positioned on the insulation material layer, and is electrically connected the chip module through the electrical interconnection. The method for manufacturing the embedded package structure also provides.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: Chia-Yen LEE, Hsin-Chang TSAI, Peng-Hsin LEE
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Publication number: 20150001692Abstract: A semiconductor component comprising a lateral semiconductor device, a vertical semiconductor device, and a leadframe is provided. The lateral semiconductor device has a first side and a second side, and a first electrode, a second electrode, and a control electrode positioned on the first side. The vertical semiconductor device has a first side and a second side, a second electrode and a control electrode of it positioned on the second side and a first electrode of it positioned on the first side. The leadframe electrically and respectively connected to each of the first electrode of the lateral semiconductor device, the second electrode of the lateral semiconductor device, the second electrode of the vertical semiconductor device, and the control electrodes, wherein the first side of the vertical semiconductor device is mounted on the second side of the lateral semiconductor device, and the first electrodes of both devices are electrically connected.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: Hsin-Chang TSAI, Chia-Yen LEE, Peng-Hsin LEE
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Patent number: 8912663Abstract: The disclosure provides an embedded package structure comprising a metal substrate, a chip module, an insulation material layer, and at least one patterned metal layer. The metal substrate has a first surface and a second surface. The chip module is disposed on the first surface of the metal substrate, and comprises at least two stacked chips being electrically connected to each. The insulation material layer covers the first surface of the metal substrate and the stacked chips and has an electrical interconnection formed therein. The patterned metal layer is positioned on the insulation material layer, and is electrically connected the chip module through the electrical interconnection. The method for manufacturing the embedded package structure also provides.Type: GrantFiled: June 28, 2013Date of Patent: December 16, 2014Assignee: Delta Electronics, Inc.Inventors: Chia-Yen Lee, Hsin-Chang Tsai, Peng-Hsin Lee
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Patent number: 8805038Abstract: This algorithm provides a marker-free approach to establishing the pixel correspondence among the IR images taken at different times, which is the basis for quantitatively characterizing the variation of the heat energy and patterns pixel-wise on a breast surface. The idea is to use the corner points of the heat pattern and the branch points of the skeletons of the heat pattern on the body surface as the initial fiducial points for the longitudinal IR image registration. The Thin-Plate Spline technique is used to model the nonlinear deformation between two IR images taken at two different times. Mutual information between the TPS-transformed image and the target image is employed as the metric quantifying the quality of the longitudinal IR image registration. To optimize the registration, Nelder-Mead simplex method is used to locally modify the pairings of the fiducial points in the source and target IR images to maximize the mutual information.Type: GrantFiled: June 30, 2011Date of Patent: August 12, 2014Assignee: National Taiwan UniversityInventors: Chung-Ming Chen, Si-Chen Lee, Wan-Jou Lee, Che-Wei Chang, Yu-Chun Chien, Chia-Yen Lee
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Patent number: 8773744Abstract: A 3D image display system with high resolution is disclosed. The system may deflect left and right eye images to a left and right eye of a viewer, respectively. As such, the viewer can see 3D images. With a time-sharing mode, all of electronically switchable light modulating cells are configured to modulate all of the images deflected to the left eye of the viewer during a first period, and modulate all of the images to the right eye of the viewer during a second period, and the first period and the second period are alternate periods. Alternatively, a part of the electronically switchable light modulating cells are configured to modulate left eye images deflected to the left eye of the viewer, and another part of the electronically switchable light modulating cells are configured to modulate right eye images to the right eye of the viewer during the same period.Type: GrantFiled: January 28, 2011Date of Patent: July 8, 2014Assignee: Delta Electronics, Inc.Inventors: Rong-Chang Liang, Ming-Wei Tsai, Ming-Hai Chang, Ching-Tung Hsu, Chia-Yen Lee, Keh-Su Chang
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Publication number: 20140185126Abstract: An electrowetting cell includes first and second substrates, a spacer, first and second electrodes, a dielectric layer, and a medium. The spacer is disposed between the first and second substrates to substrate define a compartment. The first and second electrodes are disposed on the first and second substrates respectively. The dielectric layer is formed on the first electrode. The medium is filled in the compartment and deformed in accordance with an electric potential difference between the first and second electrodes. One of the first and second electrodes is applied by a driving signal. The driving signal is divided into a plurality of driving sections in a first time period. A first driving section is changed between first and second threshold voltage levels, and a horizontal voltage level is inserted into the first driving section.Type: ApplicationFiled: December 27, 2012Publication date: July 3, 2014Applicant: DELTA ELECTRONICS, INCInventors: Rong-Chang LIANG, Ching-Tung HSU, Yeong-Feng WANG, Ming-Wei TSAI, Chia-Yen LEE, Meng-Han LIU, Yen-I CHOU
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Publication number: 20140160554Abstract: Disclosed is an image display apparatus, including a display device displaying right-eye images and left-eye images. A light-modulating device attached to the display device; and a temperature sensor monitoring the light-modulating device temperature. The light-modulating device deflects the right-eye and left-eye images to an observer's right and left eyes respectively without a temperature variation in the temperature sensor.Type: ApplicationFiled: December 12, 2012Publication date: June 12, 2014Applicant: DELTA ELECTRONICS, INC.Inventors: Yeong-Feng WANG, Ching-Tung HSU, Yen-I CHOU, Chia-Yen LEE, Meng-Han LIU, Ming-Wei TSAI
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Publication number: 20140131871Abstract: A method of forming an interconnection structure is disclosed, including providing a substrate having a first side and a second side opposite to the first side, forming a via hole through the substrate, wherein the via hole has a first opening in the first side and a second opening in the second side, forming a first pad covering the first opening, and forming a via structure in the via hole subsequent to forming the first pad, wherein the via structure includes a conductive material and is adjoined to the first pad.Type: ApplicationFiled: November 13, 2012Publication date: May 15, 2014Applicant: DELTA ELECTRONICS, INC.Inventors: Hsin-Chang TSAI, Chia-Yen LEE, Peng-Hisn LEE
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Publication number: 20140131887Abstract: A package structure including: a first semiconductor device including a first semiconductor substrate and a first electronic device, the first semiconductor device having a first side and a second side, wherein at least part of the first electronic device being adjacent to the first side, and the first semiconductor device has a via-hole formed through the first semiconductor device, wherein the via-hole has a first opening adjacent to the first side; an interconnection structure disposed in the first semiconductor device, wherein the interconnection structure includes: a via structure disposed in the via-hole without exceeding the first opening; a first pad disposed on the first side of the first semiconductor device and covering the via-hole; and a second semiconductor device vertically integrated with the first semiconductor device.Type: ApplicationFiled: September 6, 2013Publication date: May 15, 2014Applicant: DELTA ELECTRONICS, INC.Inventors: Chia-Yen LEE, Hsin-Chang TSAI, Peng-Hsin LEE
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Patent number: D732046Type: GrantFiled: January 22, 2014Date of Patent: June 16, 2015Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Chia-Yen Lee, Chia-Chieh Cheng, Wei-Che Chen
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Patent number: D741780Type: GrantFiled: October 23, 2013Date of Patent: October 27, 2015Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: Chia-Yen Lee