Chia-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.
Abstract: A semiconductor structure is provided. A first semiconductor device includes a first conductive layer formed over a first substrate; a first etching stop layer formed over the first conductive layer, and the first etching stop layer is in direct contact with the first conductive layer. A first bonding layer is formed over the first etching stop layer, and a first bonding via is formed through the first bonding layer and the first etching stop layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over the second etching stop layer and a second bonding via formed through the second bonding layer and a second etching stop layer. A bonding structure between the first substrate and the second substrate, and the bonding structure includes the first bonding via bonded to the second bonding via.
Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes a substrate, a growth promoting region, a first gate stack, and a second gate stack. The substrate includes a first region and a second region. The growth promoting region is located in a surface of the substrate in the first region. The growth promoting region includes a first implantation species, and a surface of the substrate in the second region is free of the first implantation species. The first gate stack includes a first gate dielectric layer on the substrate in the first region. The second gate stack includes a second gate dielectric layer on the substrate in the second region.
Abstract: A computer system includes an openflow switch, configured to receive a plurality of packets; a network controller, coupled to the openflow switch and configured to determine a route of each of the plurality of packets; and a detecting and defending system, configured to perform transformation of information formats of the plurality of packets, retrieve and label the plurality of packets to determine whether the plurality of packets are abnormal or not and generate a defending determination.
Abstract: A semiconductor structure includes a semiconductive substrate including a first side and a second side opposite to the first side, a radiation sensing device disposed in the semiconductive substrate, and an ILD disposed over the first side of the semiconductive substrate, and a conductive pad disposed within the semiconductive substrate and the ILD, and electrically connected to an interconnect structure. A top surface of the conductive pad is between the first side of the semiconductive substrate and the second side of the semiconductor substrate.
January 31, 2019
Date of Patent:
June 16, 2020
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.
Abstract: Systems, computer-implemented methods, and computer program products to facilitate gradient weight compression are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a pointer component that can identify one or more compressed gradient weights not present in a first concatenated compressed gradient weight. The computer executable components can further comprise a compression component that can compute a second concatenated compressed gradient weight based on the one or more compressed gradient weights to update a weight of a learning entity of a machine learning system.
Abstract: Methods of fabricating a probe are described. In an example, a structure may be formed on a surface of a substrate. The structure may include the probe, a hinge, and an anchor arranged linearly, where an angle is formed between the probe and the hinge. The hinge may be positioned between the probe and the anchor, and the structure may be parallel to the substrate. An amount of solder may be deposited on an area of the structure that spans from a portion of the probe to a portion of the anchor, and across the hinge. The deposited solder may be reshaped by an execution of a solder reflow process. The reshape of the deposited solder may cause the probe to rotate about the hinge in order to reduce the angle between the probe and the hinge.
November 30, 2018
June 4, 2020
Li-Wen Hung, Jui-Hsin Lai, Chia-Yu Chen, Ko-Tao Lee
Abstract: A hydrogenation method for increasing the yield of cyclohexane-1,4-dicarboxylic acid diisooctyl ester is provided. The hydrogenation method uses a hydrogenating reaction tank, which is equipped with a hollow-shaft gas-introducing mixer having air-extracting, air-exhausting and mixing functions, to allow hydrogen gas to be uniformly dispersed in a reaction solution. A ruthenium-on-alumina (Ru/Al2O3) hydrogenation catalyst can be used for carrying out a hydrogenation reaction under gentle conditions. Therefore, the hydrogenation catalyst can be used in a reduced amount, the risk of side reaction(s) can be reduced, and the yield of cyclohexane-1,4-dicarboxylic acid diisooctyl ester can reach at least 99% with a cis isomer proportion of at least 85.0%. The hydrogenation method shows extremely high economic benefit.
Abstract: Embodiments described herein relate generally to methods for etching structures and the structures formed thereby. In some embodiments, an etch selectivity between a first portion of a material and a second portion of the material is increased. Increasing the etch selectivity includes performing an anisotropic treatment, such as an anisotropic ion implantation, on the material to treat the first portion of the material, and the second portion of the material remains untreated after the anisotropic treatment. After increasing the etch selectivity, the first portion of the material is etched. The etching may be a wet or dry etch, and may further be isotropic or anisotropic.
Abstract: A reticle stage is provided, including an electrostatic chuck and an acoustic wave transducer. The electrostatic chuck includes multiple chucking electrodes embedded in a dielectric body and configured to secure a reticle to a chuck surface of the dielectric body by electrostatic attraction. The acoustic wave transducer is disposed on the chuck surface and configured to impart a surface acoustic wave to the chuck surface to vibrate the chuck surface, thereby removing the reticle from the reticle stage.
Abstract: A portable electronic device, an operating method for the same, and a non-transitory computer readable recording medium are provided. The portable electronic device includes a body, a touch display screen and an edge sensor. The touch display screen is disposed on the body. The edge sensor is disposed adjacent to an edge of the body. The operating method includes the following step. When an event is generated according to a first action sensed by the edge sensor, a touch function of a region of the touch display screen or the whole touch display screen is disabled.
Abstract: A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device includes orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. The mask layer and the dielectric layer are restored over the trench. P-type field-effect transistor (PFET) fins are etched on the base substrate, and N-type field-effect transistor (NFET) fins are etched in the semiconductor layer.
December 16, 2016
Date of Patent:
May 19, 2020
International Business Machines Corporation
Chia-Yu Chen, Bruce B. Doris, Hong He, Rajasekhar Venigalla
Abstract: An interconnect layout structure, having a plurality of air gaps, includes a substrate having an insulating material disposed thereon and a conductive line disposed in the insulating material and extending along a first direction. The air gaps are formed in the insulating material and are arranged end-to-end along the first direction and immediately adjacent to a same side of the conductive line. A patterned hard mask is disposed on the conductive line and has a sidewall extending along a second direction that is perpendicular to the first direction and passing between the adjacent air gaps from the top view. A via structure is formed on the conductive line and is electrically connected to the conductive line.
Abstract: A Static Random Access Memory (SRAM) device in a binary neural network is provided. The SRAM device includes an SRAM inference engine having an SRAM computation architecture with a forward path that include multiple SRAM cells. The multiple SRAM cells are configured to form a chain of SRAM cells such that an output of a given one of the multiple SRAM cells is an input to a following one of the multiple SRAM cells. The SRAM computation architecture is configured to compute a prediction from an input.
Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.
Abstract: A semiconductor package structure includes a substrate, a first semiconductor and a second semiconductor over the substrate, and a multi-TIM structure disposed over the first semiconductor die and the second semiconductor die. The first semiconductor die includes a first heat output and the second semiconductor die includes a second heat output less than the first heat output. The multi-TIM structure includes a first TIM layer disposed over at least a portion of the first semiconductor die and a second TIM layer. A thermal conductivity of the first TIM layer is higher than a thermal conductivity of the second TIM layer. The first TIM layer covers the first semiconductor die.
Abstract: Structures and techniques introduced here enable the design and fabrication of photodetectors (PDs) and/or other electronic circuits using typical semiconductor device manufacturing technologies meanwhile reducing the adverse impacts on PDs' performance. Examples of the various structures and techniques introduced here include, but not limited to, a pre-PD homogeneous wafer bonding technique, a pre-PD heterogeneous wafer bonding technique, a post-PD wafer bonding technique, their combinations, and a number of mirror equipped PD structures. With the introduced structures and techniques, it is possible to implement PDs using typical direct growth material epitaxy technology while reducing the adverse impact of the defect layer at the material interface caused by lattice mismatch.
Abstract: A method for improving performance of a predefined Deep Neural Network (DNN) convolution processing on a computing device includes inputting parameters, as input data into a processor on a computer that formalizes a design space exploration of a convolution mapping, on a predefined computer architecture that will execute the predefined convolution processing. The parameters are predefined as guided by a specification for the predefined convolution processing to be implemented by the convolution mapping and by a microarchitectural specification for the processor that will execute the predefined convolution processing. The processor calculates performance metrics for executing the predefined convolution processing on the computing device, as functions of the predefined parameters, as proxy estimates of performance of different possible design choices to implement the predefined convolution processing.
Abstract: A waveguide structure includes a first surface having a first width, a second surface having a second width, the second surface being opposite to the first surface, and a sidewall surface connecting the first surface and the second surface. The first width is greater than the second width.