Abstract: A wrench adjustable in head angle includes a pull lever having one end provided with an accommodating groove for receiving a spring and a resisting pin. The resisting pin is fitted thereon with a push member, and the pull lever is pivotally connected with a driving head. The resisting pin has one end elastically pushed by the spring to be engaged with one end of the driving head and the resisting pin is engaged with the push member. The push member can be pushed to actuate the resisting pin to press the spring, letting the resisting pin disengaged from the driving head for adjusting the angle of the driving head, convenient in operation.

Abstract: Wireless communication is established between electronic devices by an initiating device transmitting a wireless communication request to a peripheral device; the initiating device detecting a visible electromagnetic pattern displayed on the peripheral device in response to the wireless communication request; the initiating device decoding the visible electromagnetic pattern to generate a passcode; and the initiating device echoing the passcode to the peripheral device to authenticate the wireless communication request without user intervention.

Abstract: Techniques facilitating matrix multiplication on a systolic array are provided. A computer-implemented method can comprise populating, by a system operatively coupled to a processor, respective first registers of one or more processing elements of a systolic array structure with respective input data bits of a first data matrix. The one or more processing elements can comprise a first processing element that comprises a first input data bit of the first data matrix and a first activation bit of a second data matrix. The method can also include determining, by the system, at the first processing element, a first partial sum of a third data matrix. Further, the method can include streaming, by the system, the first partial sum of the third data matrix from the first processing element.

Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

Abstract: A component such as a display may have a substrate and thin-film circuitry on the substrate. The thin-film circuitry may be used to form an array of pixels for a display or other circuit structures. Metal traces may be formed among dielectric layers in the thin-film circuitry. Metal traces may be provided with insulating protective sidewall structures. The protective sidewall structures may be formed by treating exposed edge surfaces of the metal traces. A metal trace may have multiple layers such as a core metal layer sandwiched between barrier metal layers. The core metal layer may be formed from a metal that is subject to corrosion. The protective sidewall structures may help prevent corrosion in the core metal layer. Surface treatments such as oxidation, nitridation, and other processes may be used in forming the protective sidewall structures.

Abstract: A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device includes orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. The mask layer and the dielectric layer are restored over the trench. P-type field-effect transistor (PFET) fins are etched on the base substrate, and N-type field-effect transistor (NFET) fins are etched in the semiconductor layer.

Abstract: A method (and system) for generating random numbers includes setting a drain voltage Vd on an MOSFET (metal oxide semiconductor field effect transistor) device and a gate voltage Vg of the MOSFET device so that the MOSFET device comprises a noise source configured in a manner such as to tune as desired a random number statistical distribution of an output of the MOSFET device. An output voltage of the MOSFET is provided as an input signal into a low noise amplifier and an output voltage of the low noise amplifier provides values for a random number generator.

Abstract: The present invention relates to a ratchet wrench which comprises a head portion having an installation chamber for a ratchet gear, a control chamber for a switching unit, a control chamber for a switching unit and a ratchet chamber for a ratchet block. The ratchet chamber is formed in between the installation chamber and the control chamber. The ratchet wrench further comprises a base plate having a limit member chamber formed thereon and having a first limit wall and a second limit wall. There is a limit member installed in the control chamber and has a push portion formed thereon. The characteristic feature of the ratchet wrench is that the switching unit having a push portion formed thereon to match with the first limit wall or the second limit wall of the limit member chamber.

Abstract: An apparatus and method for supporting simultaneous multiple iterations (SMI) in a course grained reconfigurable architecture (CGRA). In support of SMI, the apparatus includes: Hardware structures that connect all of multiple processing engines (PEs) to a load-store unit (LSU) configured to keep track of which compiled program code iterations have completed, which ones are in flight and which are yet to begin, and a control unit including hardware structures that are used to maintain synchronization and initiate and terminate loops within the PEs. SMI permits execution of the next instruction within any iteration (in flight). If instructions from multiple iterations are ready for execution (and are pre-decoded), then the hardware selects the lowest iteration number ready for execution. If in a particular clock cycle, a loop iteration with a lower iteration number is stalled (i.e.

Abstract: A method (and system) for generating random numbers includes setting a drain voltage Vd on an MOSFET device to maximize a transconductance of the MOSFET device and setting a gate voltage Vg of the MOSFET device to tune as desired a random number statistical distribution of an output of the MOSFET device. The MOSFET device includes a gate structure with an oxide layer including at least one artificial trapping layer in which carrier traps are designed to occupy a predetermined distance from conduction and valance bands of material of the artificial trapping layer.

Abstract: Techniques facilitating matrix multiplication on a systolic array are provided. A computer-implemented method can comprise populating, by a system operatively coupled to a processor, respective first registers of one or more processing elements of a systolic array structure with respective input data bits of a first data matrix. The one or more processing elements can comprise a first processing element that comprises a first input data bit of the first data matrix and a first activation bit of a second data matrix. The method can also include determining, by the system, at the first processing element, a first partial sum of a third data matrix. Further, the method can include streaming, by the system, the first partial sum of the third data matrix from the first processing element.

Abstract: Techniques facilitating matrix multiplication on a systolic array are provided. A computer-implemented method can comprise populating, by a system operatively coupled to a processor, respective first registers of one or more processing elements of a systolic array structure with respective input data bits of a first data matrix. The one or more processing elements can comprise a first processing element that comprises a first input data bit of the first data matrix and a first activation bit of a second data matrix. The method can also include determining, by the system, at the first processing element, a first partial sum of a third data matrix. Further, the method can include streaming, by the system, the first partial sum of the third data matrix from the first processing element.

Abstract: A reversing ratchet wrench includes a head, a ratchet wheel, a ratchet block, a change-over unit and a position-limiting member. The position-limiting member is transversely fixed at the underside of the change-over unit, and the change-over unit has its upper end provided with an actuating member, which can be turned to actuate the position-limiting member to rotate. When the position-limiting member is actuated by the actuating member to lie at a first position, the first stop end of the position-limiting member will be stopped at the inner wall of one side of a ring groove and, when the position-limiting member is actuated to lie at a second position, the second stop end will be stopped at the inner wall of another side of the ring groove. Thus, the actuating member can be restrictedly positioned via the position-limiting member.

Abstract: A high torque ratchet wrench comprises a head portion having a chamber for the installation of a driving gear, a slot for the installation of a controller which comprises a control body having a recess for storing an elastic member, and a pressing pin. A ratchet block has a plurality of ratchet teeth formed thereon, a curvature section being contacted by the pressing pin of the controller, and a pair of pressing surface sections. The chamber in the head portion comprises a pair of holding surface sections corresponding to the pressing surface sections of the ratchet block. The driving gear having a radius substantially equal to the same of the ratchet teeth of the ratchet block thereby the ratchet teeth of the ratchet block will be substantially matched with the gear teeth of the driving gear.

Abstract: Frequency division multiplexing-based techniques for FET-based sensor arrays are provided. In one aspect, a sensor device includes: an array of FET-based sensors, wherein the sensors are grouped into multiple channels, and wherein each of the sensors includes an insulator on a substrate, a local gate embedded in the insulator, a channel material over the local embedded gate, and source and drain electrodes in contact with opposite ends of the channel material, and wherein a surface of the channel material is functionalized to react with at least one target molecule. The sensors in a given channel can be modulated (via the local gate) to enable the signal read out from the channel to be divided in the frequency domain based on the different frequencies used to modulate the sensors.

Abstract: A method of forming a metal-insulator-semiconductor (MIS) contact, a transistor including the MIS contact, and the MIS contact are described. The method includes etching an opening for formation of the contact, the opening extending to an upper surface of a semiconductor region. The method also includes implanting metal ions at a selected depth within the upper surface of the semiconductor region and converting the upper surface of the semiconductor region to a metal oxide insulating layer. The method further includes forming a metal layer on the insulating layer.

Abstract: A method of forming a metal-insulator-semiconductor (MIS) contact, a transistor including the MIS contact, and the MIS contact are described. The method includes etching an opening for formation of the contact, the opening extending to an upper surface of a semiconductor region. The method also includes implanting metal ions at a selected depth within the upper surface of the semiconductor region and converting the upper surface of the semiconductor region to a metal oxide insulating layer. The method further includes forming a metal layer on the insulating layer.

Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

Abstract: Wireless communication is established between electronic devices by an initiating device transmitting a wireless communication request to a peripheral device; the initiating device detecting a visible electromagnetic pattern displayed on the peripheral device in response to the wireless communication request; the initiating device decoding the visible electromagnetic pattern to generate a passcode; and the initiating device echoing the passcode to the peripheral device to authenticate the wireless communication request without user intervention.

Abstract: A random number signal generator used for performing dropout or weight initialization for a node in a neural network. The random number signal generator includes a transistor which generates a random noise signal. The transistor includes a substrate, source and drain regions formed in the substrate, a first insulating layer formed over a channel of the transistor, a first trapping layer formed over the first insulating layer, a second insulating layer formed over the first trapping layer, and a second trapping layer formed over the second insulating layer. One or more traps in the first and second trapping layers are configured to capture or release one or more carriers flowing through the channel region. The random noise signal is generated as a function of one or more carrier being captured or released by the one or more traps.