Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: A physical vapor deposition (PVD) target for performing a PVD process is provided. The PVD target includes a backing plate and a target plate coupled to the backing plate. The target plate includes a sputtering source material and a dopant, with the proviso that the dopant is not impurities in the sputtering source material. The sputtering source material includes a diffusion barrier material.

Abstract: A physical vapor deposition (PVD) system includes: a chamber body; a substrate support disposed within the chamber body and capable of supporting a substrate; a PVD target; and a target profile monitoring subsystem. The PVD target includes: a target plate comprising a target material; and a backing plate attached to the target plate and comprising: a central section; and a peripheral section circumferentially surrounding the central section in a horizontal plane. The peripheral section has a first thickness in a vertical direction, the central section has a second thickness in the vertical direction, and the first thickness is larger than the second thickness. The target profile monitoring subsystem is configured to monitor usage of the target plate.

Abstract: Various embodiments of the present application are directed toward an adjustable wafer chuck. The adjustable wafer chuck is configured to hold a wafer. The adjustable wafer chuck comprises a base portion and a pad portion. The base portion comprises a plurality of adjustable base structures. The pad portion is disposed on a first side of the base portion. The pad portion comprises a plurality of contact pads disposed on the plurality of adjustable base structures. Each of the adjustable base structures are configured to move along a plane in a first direction and configured to move along the plane in a second direction that is opposite the first direction.

Abstract: A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.

Abstract: Embodiments of the present disclosure provide semiconductor devices having conductive features with reduced height and increased width, and methods for forming the semiconductor devices. Particularly, sacrificial self-aligned contact (SAC) layer and sacrificial metal contact etch stop layer (M-CESL) are used to form conductive features with reduced resistance. After formation of the conductive features, the sacrificial SAC and sacrificial M-CESL are removed and replaced with a low-k material to reduce capacitance in the device. As a result, performance of the device is improved.

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: A semiconductor structure includes a metal gate structure including a gate dielectric layer and a gate electrode, a conductive layer disposed on the gate electrode, and a gate contact disposed on the conductive layer. The conductive layer extends from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure. The gate electrode includes at least a first metal, and the conductive layer includes at least the first metal and a second metal different from the first metal. Laterally the conductive layer is fully between opposing sidewalls of the metal gate structure.

Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor on a substrate, a contact electrically connected to a source/drain feature of the transistor, a first dielectric layer on a gate stack of the transistor, a second dielectric layer on the contact, a gate spacer layer between the gate stack of the transistor and the contact, and a contact liner between the gate spacer layer and the contact. A top of the contact liner is located higher than a bottom surface of the second dielectric layer and lower than a top surface of the second dielectric layer.

Abstract: A method includes forming a device region over a substrate; forming a first dielectric layer over the device region; forming an opening in the first dielectric layer; conformally depositing a first conductive material along sidewalls and bottom surfaces of the opening; depositing a second conductive material on the first conductive material to fill the opening, wherein the second conductive material is different from the first conductive material; and performing a first thermal process to form an interface region extending from a first region of the first conductive material to a second region of the second conductive material, wherein the interface region includes a homogeneous mixture of the first conductive material and the second conductive material.

Abstract: A formulation comprising TML-6 or a pharmaceutically acceptable salt, solvate, hydrate, or prodrug thereof in an amorphous form, and one or more excipients,

Abstract: An electronic package and a substrate structure thereof are provided, in which an electronic element and a flow stopper surrounding the electronic element are disposed on a substrate body of the substrate structure, and a heat dissipation structure is bonded on the electronic element via a heat dissipation material, so that the flow stopper limits an overflow range of the heat dissipation material to prevent the heat dissipation material from contaminating a circuit layer on the substrate body.

Abstract: An immersion cooling system includes a cooling tank, a sensor and two control chips. The first control chip includes a first heartbeat circuit configured to periodically send a first heartbeat signal, a first watchdog circuit configured to real-time monitor the status of the first control circuit and a second heartbeat signal, a first data sensing port for selectively reading data measured by the sensor, and a first data transmitting port for selectively outputting data read by the first data sensing port. The second control chip includes a second heartbeat circuit configured to periodically send the second heartbeat signal, a second watchdog circuit configured to real-time monitor the status of the second control circuit and the first heartbeat signal, a second data sensing port for selectively reading data measured by the sensor, and a second data transmitting port for selectively outputting data read by the second data sensing port.

Abstract: A semiconductor structure includes a substrate; a first structure over the substrate and having a first gate stack and two first gate spacers on two opposing sidewalls of the first gate stack; a second structure over the substrate and having a second gate stack and two second gate spacers on two opposing sidewalls of the second gate stack; a source/drain (S/D) feature over the substrate and adjacent to the first and the second gate stacks; an S/D contact over the S/D feature and between one of the first gate spacers and one of the second gate spacers; a conductive via disposed over and electrically connected to the S/D contact; and a dielectric liner layer. A first portion of the dielectric liner layer is disposed on a sidewall of the one of the first gate spacers and is directly above the S/D contact and spaced from the S/D contact.

Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor substrate includes a semiconductor material over a base substrate. The semiconductor substrate has one or more sidewalls forming a crack stop trench that is laterally between a central region of the semiconductor substrate and a peripheral region of the semiconductor substrate that surrounds the central region. The peripheral region of the semiconductor substrate includes a plurality of cracks.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a conductive structure disposed over the device, and the conductive structure includes a sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer including a third portion and a fourth portion, the third portion surrounds the first portion of the sidewall, and the fourth portion is disposed on the conductive structure. The semiconductor device structure further includes a first dielectric material surrounding the third portion, and an air gap is formed between the first dielectric material and the third portion of the first spacer layer. The first dielectric material includes a first material different than a second material of the first spacer layer, and the first dielectric material is substantially coplanar with the fourth portion of the first spacer layer.