Patents by Inventor Chia-Yu WEI

Chia-Yu WEI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220293650
    Abstract: A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures in a first direction. The semiconductor device further includes a gate structure. The gate structure includes a top surface; a first sidewall angled at a non-perpendicular angle with respect to the top surface; and a second sidewall angled with respect to the top surface. The gate structure further includes a first horizontal surface extending between the first sidewall and the second sidewall, wherein the first horizontal surface is parallel to the top surface, and a dimension of the gate structure in a second direction, perpendicular to the first direction, is less than a dimension of each of the plurality of isolation structures in the second direction.
    Type: Application
    Filed: June 2, 2022
    Publication date: September 15, 2022
    Inventors: Chia-Yu WEI, Fu-Cheng CHANG, Hsin-Chi CHEN, Ching-Hung KAO, Chia-Pin CHENG, Kuo-Cheng LEE, Hsun-Ying HUANG, Yen-Liang LIN
  • Publication number: 20220271071
    Abstract: A backside illuminated image sensor device with a shielding layer and a manufacturing method thereof are provided. In the backside illuminated image senor device, a patterned conductive shielding layer is formed on a dielectric layer on a backside surface of a semiconductor substrate and surrounding a pixel array on a front side surface of the semiconductor substrate.
    Type: Application
    Filed: May 13, 2022
    Publication date: August 25, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Volume CHIEN, Su-Hua CHANG, Chia-Yu WEI, Zen-Fong HUANG, Chi-Cherng JENG
  • Publication number: 20220230064
    Abstract: An analog circuit is calibrated to perform neural network computing. Calibration input is provided to a pre-trained neural network that includes at least a given layer having pre-trained weights stored in the analog circuit. The analog circuit performs tensor operations of the given layer using the pre-trained weights. Statistics of calibration output from the analog circuit is calculated. Normalization operations to be performed during neural network inference are determined. The normalization operations incorporate the statistics of the calibration output and are performed at a normalization layer that follows the given layer. A configuration of the normalization operations is written into memory while the pre-trained weights stay unchanged.
    Type: Application
    Filed: January 6, 2022
    Publication date: July 21, 2022
    Inventors: Po-Heng Chen, Chia-Da Lee, Chao-Min Chang, Chih Chung Cheng, Hantao Huang, Pei-Kuei Tsung, Chun-Hao Wei, Ming Yu Chen
  • Patent number: 11380721
    Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: July 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Yu Wei, Fu-Cheng Chang, Hsin-Chi Chen, Ching-Hung Kao, Chia-Pin Cheng, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
  • Patent number: 11335721
    Abstract: A backside illuminated image sensor device with a shielding layer and a manufacturing method thereof are provided. In the backside illuminated image senor device, a patterned conductive shielding layer is formed on a dielectric layer on a backside surface of a semiconductor substrate and surrounding a pixel array on a front side surface of the semiconductor substrate.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: May 17, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Volume Chien, Su-Hua Chang, Chia-Yu Wei, Zen-Fong Huang, Chi-Cherng Jeng
  • Publication number: 20220077206
    Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a substrate and a transfer gate disposed from a front-side surface of the substrate. The CMOS image sensor further comprises a photo detecting column disposed at one side of the transfer gate within the substrate. The photo detecting column comprises a doped sensing layer comprising one or more recessed portions along a circumference of the doped sensing layer in parallel to the front-side surface of the substrate. By forming the photo detecting column with recessed portions, a junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.
    Type: Application
    Filed: November 17, 2021
    Publication date: March 10, 2022
    Inventors: Chia-Yu Wei, Hsin-Chi Chen, Kuo-Cheng Lee, Ping-Hao Lin, Hsun-Ying Huang, Yen-Liang Lin, Yu Ting Kao
  • Publication number: 20220052100
    Abstract: The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform. Anchor structures can include anchor layers formed on a dielectric layer surface and anchor pads formed in the anchor layer and on the dielectric layer surface. The anchor layer material can be selected such that the planarization selectivity of the anchor layer, anchor pads, and the interconnection material can be substantially the same as one another. Anchor pads can provide uniform density of structures that have the same or similar material.
    Type: Application
    Filed: October 18, 2021
    Publication date: February 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu Wei, Cheng-Yuan Li, Hsin-Chi Chen, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
  • Patent number: 11189743
    Abstract: A photodetector includes: a substrate; a first semiconductor region, the first semiconductor region extending into the substrate from a front side of the substrate; and a second semiconductor region, the second semiconductor region further extending into the substrate from a bottom boundary of the first semiconductor region, wherein when the photodetector operates under a Geiger mode, the second semiconductor region is fully depleted to absorb a radiation source received from a back side of the substrate.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu Wei, Yu-Ting Kao, Yen-Liang Lin, Wen-I Hsu, Hsun-Ying Huang, Kuo-Cheng Lee, Hsin-Chi Chen
  • Publication number: 20210366953
    Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first component in a substrate. The semiconductor arrangement includes a gap fill layer. A first portion of the gap fill layer overlies the first component. The first portion of the gap fill layer has a tapered sidewall. A first portion of the substrate separates the first portion of the gap fill layer from the first component.
    Type: Application
    Filed: May 21, 2020
    Publication date: November 25, 2021
    Inventors: Chia Jung HSU, Chia-Yu Wei, Kuo-Cheng Lee, Chen Ying-Hao
  • Patent number: 11183523
    Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a floating diffusion region disposed at one side of a transfer gate within a substrate and a photo detecting column disposed at the other side of the transfer gate opposing to the floating diffusion region within the substrate. The photo detecting column comprises a doped sensing layer with a doping type opposite to that of the substrate. The photo detecting column and the substrate are in contact with each other at a junction interface comprising one or more recessed portions. By forming the junction interface with recessed portions, the junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Yu Wei, Hsin-Chi Chen, Kuo-Cheng Lee, Ping-Hao Lin, Hsun-Ying Huang, Yen-Liang Lin, Yu Ting Kao
  • Patent number: 11152417
    Abstract: The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform. Anchor structures can include anchor layers formed on a dielectric layer surface and anchor pads formed in the anchor layer and on the dielectric layer surface. The anchor layer material can be selected such that the planarization selectivity of the anchor layer, anchor pads, and the interconnection material can be substantially the same as one another. Anchor pads can provide uniform density of structures that have the same or similar material.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu Wei, Cheng-Yuan Li, Hsin-Chi Chen, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
  • Publication number: 20210202564
    Abstract: A method includes providing a semiconductor substrate having a front side surface and a back side surface opposite to the front side surface. A photosensitive region of the semiconductor substrate is etched to form a recess. A semiconductor material is deposited on the semiconductor substrate to form a radiation sensing member filling the recess. The semiconductor material has an optical band gap energy smaller than 1.77 eV. A device layer is formed over the front side surface of the semiconductor substrate and the radiation sensing member. A trench isolation is formed in an isolation region of the semiconductor substrate and extending from the back side surface of the semiconductor substrate.
    Type: Application
    Filed: February 24, 2021
    Publication date: July 1, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu WEI, Yen-Liang LIN, Kuo-Cheng LEE, Hsun-Ying HUANG, Hsin-Chi CHEN
  • Patent number: 11018179
    Abstract: A semiconductor structure includes an ILD disposed over a semiconductive substrate, an isolation disposed between the semiconductive substrate and the ILD, and a conductive pad disposed within the semiconductive substrate, the isolation and the ILD. A top surface of the conductive pad is substantially parallel with two surfaces of the semiconductive substrate. The top surface of the conductive pad is between the two surfaces of the semiconductive substrate. Sidewalls of the conductive pad are in direct contact with the ILD and the isolation.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Yu Wei, Chin-Hsun Hsiao, Yi-Hsing Chu, Yen-Liang Lin, Yung-Lung Hsu, Hsin-Chi Chen
  • Patent number: 10943942
    Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a device layer and a trench isolation. The semiconductor substrate has a front side surface and a back side surface opposite to the front side surface. The radiation sensing member is disposed in a photosensitive region of the semiconductor substrate and extends from the front side surface of the semiconductor substrate. The radiation sensing member includes a semiconductor material with an optical band gap energy smaller than 1.77 eV. The device layer is over the front side surface of the semiconductor substrate and the radiation sensing member. The trench isolation is disposed in an isolation region of the semiconductor substrate and extends from the back side surface of the semiconductor substrate.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu Wei, Yen-Liang Lin, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen
  • Publication number: 20200321294
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first bonding layer formed below a first substrate, a first bonding via formed through the first oxide layer and the first bonding layer, a first dummy pad formed in the first bonding layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over a second substrate, a second bonding via formed through the second bonding layer, and a second dummy pad formed in the second bonding layer. The semiconductor structure includes a bonding structure between the first substrate and the second substrate, wherein the bonding structure includes the first bonding via bonded to the second bonding via and the first dummy pad bonded to the second dummy pad.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu WEI, Cheng-Yuan LI, Yen-Liang LIN, Kuo-Cheng LEE, Hsun-Ying HUANG, Hsin-Chi CHEN
  • Patent number: 10790321
    Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a floating diffusion region disposed at one side of a transfer gate within a substrate and a photo detecting column disposed at the other side of the transfer gate opposing to the floating diffusion region within the substrate. The photo detecting column comprises a doped sensing layer with a doping type opposite to that of the substrate. The photo detecting column and the substrate are in contact with each other at a junction interface comprising one or more recessed portions. By forming the junction interface with recessed portions, the junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu Wei, Hsin-Chi Chen, Kuo-Cheng Lee, Ping-Hao Lin, Hsun-Ying Huang, Yen-Liang Lin, Yu Ting Kao
  • Publication number: 20200303435
    Abstract: A semiconductor structure includes an ILD disposed over a semiconductive substrate, an isolation disposed between the semiconductive substrate and the ILD, and a conductive pad disposed within the semiconductive substrate, the isolation and the ILD. A top surface of the conductive pad is substantially parallel with two surfaces of the semiconductive substrate. The top surface of the conductive pad is between the two surfaces of the semiconductive substrate. Sidewalls of the conductive pad are in direct contact with the ILD and the isolation.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Inventors: CHIA-YU WEI, CHIN-HSUN HSIAO, YI-HSING CHU, YEN-LIANG LIN, YUNG-LUNG HSU, HSIN-CHI CHEN
  • Publication number: 20200212244
    Abstract: A photodetector includes: a substrate; a first semiconductor region, the first semiconductor region extending into the substrate from a front side of the substrate; and a second semiconductor region, the second semiconductor region further extending into the substrate from a bottom boundary of the first semiconductor region, wherein when the photodetector operates under a Geiger mode, the second semiconductor region is fully depleted to absorb a radiation source received from a back side of the substrate.
    Type: Application
    Filed: March 13, 2020
    Publication date: July 2, 2020
    Inventors: Chia-Yu WEI, Yu-Ting KAO, Yen-Liang LIN, Wen-I HSU, Hsun-Ying HUANG, Kuo-Cheng LEE, Hsin-Chi CHEN
  • Patent number: 10692826
    Abstract: A semiconductor structure is provided. A first semiconductor device includes a first conductive layer formed over a first substrate; a first etching stop layer formed over the first conductive layer, and the first etching stop layer is in direct contact with the first conductive layer. A first bonding layer is formed over the first etching stop layer, and a first bonding via is formed through the first bonding layer and the first etching stop layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over the second etching stop layer and a second bonding via formed through the second bonding layer and a second etching stop layer. A bonding structure between the first substrate and the second substrate, and the bonding structure includes the first bonding via bonded to the second bonding via.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu Wei, Cheng-Yuan Li, Yen-Liang Lin, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen
  • Patent number: 10686005
    Abstract: A semiconductor structure includes a semiconductive substrate including a first side and a second side opposite to the first side, a radiation sensing device disposed in the semiconductive substrate, and an ILD disposed over the first side of the semiconductive substrate, and a conductive pad disposed within the semiconductive substrate and the ILD, and electrically connected to an interconnect structure. A top surface of the conductive pad is between the first side of the semiconductive substrate and the second side of the semiconductor substrate.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Yu Wei, Chin-Hsun Hsiao, Yi-Hsing Chu, Yen-Liang Lin, Yung-Lung Hsu, Hsin-Chi Chen