Patents by Inventor Chia-Yuan Chang

Chia-Yuan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12080342
    Abstract: A memory device is provided. The memory device includes a memory cell array having a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of columns include a first plurality of memory cells connected to a first bit line and a second bit line. A pre-charge circuit is connected to the memory cell array. The pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end. A pre-charge assist circuit is connected to the memory cell array. The pre-charge assist circuit pre-charges each of the first bit line and the second bit line from a second end, the second end being opposite the first end.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: September 3, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Pao, Kian-Long Lim, Chih-Chuan Yang, Jui-Wen Chang, Chao-Yuan Chang, Feng-Ming Chang, Lien-Jung Hung, Ping-Wei Wang
  • Publication number: 20240284088
    Abstract: An information handling system headset has an earcup that rotationally couples a microphone boom at one end of a cavity to rotate between an extended position with a member of the microphone boom in straight form and a retracted position with the member bent to fit in the cavity and substantially conform with the earcup periphery. The microphone boom member rotates between first and second stops disposed proximate the hinge and bend when pushed against the first stop to fit in the cavity. The microphone boom can fully insert into the cavity to have a flush outer periphery at the earcup or can partially extend out of the cavity at the terminating end where the microphone couples to the member.
    Type: Application
    Filed: February 22, 2023
    Publication date: August 22, 2024
    Applicant: Dell Products L.P.
    Inventors: Chia-Yuan Chang, You-Yu Lin, Sok Hui Khoo
  • Publication number: 20240282083
    Abstract: A method for evaluating data to be used to train an object recognition model is to be implemented by a computing device. The computing device stores a plurality of training datasets respectively related to a plurality of images, and each training dataset includes a plurality of entries of training data. The method includes steps of: obtaining, for each image, at least one target area and at least one target property that are related to the image based on the entries of training data; creating, for each image, a training material that includes the image, and the at least one target area and the at least one target property both related to the image; and obtaining at least three object recognition models based on the training materials that are created respectively for the images using at least one machine learning algorithm.
    Type: Application
    Filed: September 6, 2023
    Publication date: August 22, 2024
    Inventors: Paul Yuan-Bao SHIEH, Yi-Hsuan CHEN, Thiam-Sun PANG, Chia-I CHENG, Hung-Yu CHIEN, Hsin-Yu CHANG
  • Patent number: 12068262
    Abstract: A semiconductor package includes: a first die; a second die stacked on an upper surface of the first die, the second die including a second semiconductor substrate and a second seal ring structure that extends along a perimeter of the second semiconductor substrate; a third die stacked on the upper surface of the first die, the third die including a third semiconductor substrate and a third seal ring structure that extends along a perimeter of the third semiconductor substrate; and a connection circuit that extends through the second seal ring structure and the third seal ring structure, in a lateral direction perpendicular to the stacking direction of the first die and the second die, to electrically connect the second semiconductor substrate and the third semiconductor substrate.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jen-Yuan Chang, Chia-Ping Lai
  • Publication number: 20240245037
    Abstract: A multi-use monitoring system is disclosed, which comprises an electronic device, multiple sensor devices, multiple cameras, at least one wireless interface, and a remote electronic device. According to the present invention, the sensor devices are adopted for detecting multiple environmental parameters such as gas level, humidity and temperature, and the multiple cameras are controlled to acquire images from the poultry bred in a breeding environment. Therefore, after receiving the images and the environmental parameters from the electronic device, the remote electronic device can extract at least one poultry characteristic from the images, and then correlate the environmental parameters to the poultry characteristic(s). As a result, the remote electronic device can subsequently calculate an evaluation score according to the growth and/or health state of the poultry, such that the breeder can plan how to distribute the breeding resources for the poultry.
    Type: Application
    Filed: January 22, 2024
    Publication date: July 25, 2024
    Applicant: CALYX, INC.
    Inventors: Po-Jui CHIU, Benson FAN, Ming-Yuan TSAI, I-Ting CHEN, Chia-Cheng LIAO, Shin-Kai MA, Tsung-Lin LU, Chan-Hsin YEH, To-An TING, Ting-Shuo CHANG
  • Patent number: 12040242
    Abstract: A three-dimensional device structure includes a first die, a second die disposed on the first die, and a connection circuit. The first die includes a first semiconductor substrate, a first interconnect structure disposed on the first semiconductor substrate, and a first seal ring surrounding the interconnect structure. The second die includes a second semiconductor substrate, a second interconnect structure disposed on the second semiconductor substrate, and a second seal ring surrounding the interconnect structure. The first connection circuit electrically couples the first seal ring to the second seal ring to provide an electrostatic discharge path.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jen-Yuan Chang, Chien-Chang Lee, Chia-Ping Lai
  • Patent number: 12014009
    Abstract: A method for obtaining a handwriting trajectory is provided. The method includes the following steps: capturing images of handwriting that is written with a writing brush on a piece of paper on a writing platform; obtaining positions where pixels in each of the images are lower than a threshold according to the threshold; and outputting handwriting images according to the positions.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: June 18, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chia-Yuan Chang, Jung-Wen Chang, Chin-Kang Chang, Ming-Yu Huang
  • Patent number: 12015066
    Abstract: A method includes providing first and second channel layers in NMOS and PMOS regions respectively of a substrate; depositing a first layer comprising hafnium oxide over the first and second channel layers; forming a first dipole pattern over the second channel layer and not over the first channel layer; driving a first metal from the first dipole pattern into the first layer by annealing; removing the first dipole pattern; depositing a second layer comprising hafnium oxide over the first layer and over the first and second channel layers; forming a second dipole pattern over the second layer and the first channel layer and not over the second channel layer; driving a second metal from the second dipole pattern into the second layer by annealing; removing the second dipole pattern; and depositing a third layer comprising hafnium oxide over the second layer and over the first and the second channel layers.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yuan Chang, Te-Yang Lai, Kuei-Lun Lin, Xiong-Fei Yu, Chi On Chui, Tsung-Da Lin, Cheng-Hao Hou
  • Publication number: 20240061703
    Abstract: A transaction merging method for a first electronic device and a second electronic device. The transaction merging method comprises: (a) receiving a plurality of input transactions from the first electronic device; (b) setting a merge condition of the input transactions according to a transmission condition between the first electronic device and the second electronic device; (c) merging the input transactions according to the merge condition to generate at least one transaction group; and (d) transmitting the transaction group to the second electronic device.
    Type: Application
    Filed: August 9, 2023
    Publication date: February 22, 2024
    Applicant: MEDIATEK INC.
    Inventors: En-Shou Tang, Yuan-Chun Lin, Ming-Lun Hsieh, Chia-Yuan Chang
  • Publication number: 20240021693
    Abstract: A semiconductor device a method of forming the same are provided. The method includes forming a fin extending from a substrate and forming a gate dielectric layer along a top surface and sidewalls of the fin. A first thickness of the gate dielectric layer along the top surface of the fin is greater than a second thickness of the gate dielectric layer along the sidewalls of the fin.
    Type: Application
    Filed: August 8, 2023
    Publication date: January 18, 2024
    Inventors: Kuei-Lun Lin, Yen-Fu Chen, Po-Ting Lin, Chia-Yuan Chang, Xiong-Fei Yu, Chi On Chui
  • Patent number: 11876122
    Abstract: A method of forming a semiconductor device. A substrate having a fin structure is provided. A dummy gate is formed on the fin structure. A polymer block is formed adjacent to a corner between the dummy gate and the fin structure. The polymer block is subjected to a nitrogen plasma treatment, thereby forming a nitridation layer in proximity to a sidewall of the dummy gate under the polymer block. After subjecting the polymer block to the nitrogen plasma treatment, a seal layer is formed on the sidewall of the dummy gate and on the polymer block. An epitaxial layer is then grown on a source/drain region of the fin structure. The dummy gate is then replaced with a metal gate.
    Type: Grant
    Filed: November 27, 2022
    Date of Patent: January 16, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wei Chang, Chia-Ming Kuo, Po-Jen Chuang, Fu-Jung Chuang, Shao-Wei Wang, Yu-Ren Wang, Chia-Yuan Chang
  • Patent number: D1009261
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: December 26, 2023
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chia-Yuan Chang, Jung-Wen Chang, Kao-Yu Hsu
  • Patent number: D1013165
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: January 30, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Barry Lam, Chia-Yuan Chang, Jung-Wen Chang, Kao-Yu Hsu
  • Patent number: D1016282
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: February 27, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Barry Lam, Chia-Yuan Chang, Jung-Wen Chang, Juan-Jung Li
  • Patent number: D1016283
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: February 27, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Barry Lam, Chia-Yuan Chang, Jung-Wen Chang, Kao-Yu Hsu
  • Patent number: D1022213
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: April 9, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Barry Lam, Chia-Yuan Chang, Jung-Wen Chang, Kao-Yu Hsu
  • Patent number: D1030517
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: June 11, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Barry Lam, Chia-Yuan Chang, Jung-Wen Chang, Juan-Jung Li
  • Patent number: D1031981
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: June 18, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Barry Lam, Chia-Yuan Chang, Jung-Wen Chang, Kao-Yu Hsu
  • Patent number: D1033653
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: July 2, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chia-Yuan Chang, Jung-Wen Chang, Juan-Jung Li
  • Patent number: D1035882
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: July 16, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Barry Lam, Chia-Yuan Chang, Jung-Wen Chang, Juan-Jung Li